Computer system initialization via boot code stored in a non-volatile memory having an interface compatible with synchronous dynamic random access memory
First Claim
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1. A computer system comprising:
- a central processor;
a system reset generator coupled to said central processor for asserting a reset signal;
a system controller coupled to said central processor and said system reset generator, wherein said system controller comprises an SDRAM memory controller and a non-volatile memory controller;
addressable non-volatile memory coupled to said system controller, said system reset generator and said central processor, wherein said non-volatile memory comprises a sequential boot logic section;
a data bus coupled between said system controller and said non-volatile memory;
an SDRAM control signal line coupled between said SDRAM memory controller and said non-volatile memory, said SDRAM control signal line for carrying SDRAM control signals;
a first control signal line coupled directly between said non-volatile memory controller and said non-volatile memory for transmitting a chip select signal from said non-volatile memory controller in response to said reset signal, wherein said chip select signal is for initiating a first read operation of a first data word at a first address in a first accessed row of said non-volatile memory; and
a second control signal line coupled directly between said non-volatile memory controller and said sequential boot logic section for transmitting a read enable signal to said non-volatile memory, wherein said read enable signal is for causing said non-volatile memory to deliver data words sequentially to said data bus beginning with said first data word, and wherein said sequentially delivered data words are for initializing an SDRAM interface of said non-volatile memory for normal operation with said computer system.
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Abstract
A method for reducing the number of interface lines and non-volatile memory devices in a computer system includes providing a non-volatile memory having a SDRAM style interface. A system having both non-volatile memory and SDRAM has reduced interface lines by providing only one memory interface. A system where the SDRAM interface logic is initialized by code stored in the non-volatile memory having a SDRAM style interface, eliminating any requirement for other non-volatile memory, independent of the SDRAM interface, from which to initialize the system.
38 Citations
19 Claims
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1. A computer system comprising:
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a central processor; a system reset generator coupled to said central processor for asserting a reset signal; a system controller coupled to said central processor and said system reset generator, wherein said system controller comprises an SDRAM memory controller and a non-volatile memory controller; addressable non-volatile memory coupled to said system controller, said system reset generator and said central processor, wherein said non-volatile memory comprises a sequential boot logic section; a data bus coupled between said system controller and said non-volatile memory; an SDRAM control signal line coupled between said SDRAM memory controller and said non-volatile memory, said SDRAM control signal line for carrying SDRAM control signals; a first control signal line coupled directly between said non-volatile memory controller and said non-volatile memory for transmitting a chip select signal from said non-volatile memory controller in response to said reset signal, wherein said chip select signal is for initiating a first read operation of a first data word at a first address in a first accessed row of said non-volatile memory; and a second control signal line coupled directly between said non-volatile memory controller and said sequential boot logic section for transmitting a read enable signal to said non-volatile memory, wherein said read enable signal is for causing said non-volatile memory to deliver data words sequentially to said data bus beginning with said first data word, and wherein said sequentially delivered data words are for initializing an SDRAM interface of said non-volatile memory for normal operation with said computer system. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of configuring a non-volatile memory in a computer system, said method comprising:
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issuing a system reset signal from a system reset generator upon booting of said computer system; receiving an initial memory read address in a system controller, said initial memory read address supplied by said central processor; issuing a chip select signal from a non-volatile memory controller of said system controller, wherein said chip select signal is issued to a non-volatile memory for initiating a first read operation of a first data word at a first address in a first accessed row of said non-volatile memory; reading said first data word; issuing a read enable signal from said non-volatile memory controller, wherein said read enable signal is issued to said non-volatile memory for causing said non-volatile memory to deliver data words sequentially to a data bus beginning with said first data word; outputting sequential data words from said non-volatile memory beginning with said first data word, said sequential data words being output from a sequential boot logic section of said non-volatile memory; and initializing an SDRAM interface of said non-volatile memory for normal operation with said computer system, wherein said initializing is performed in response to data from said sequentially output data words. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification