Scan-based state save and restore method and system for inactive state power reduction
First Claim
Patent Images
1. A circuit having scan circuitry comprising:
- a constant power area that receives constant power;
a switched power area that receives interruptible power;
wherein the switched power area includes an input for receiving a normal mode clock signal; and
an inactive state power reduction manager disposed in the constant power area for receiving a sleep signal and responsive thereto for asserting a stop clock signal to stop the normal mode clock, for performing a scan-based state-save by employing the scan circuitry, and for asserting a power control signal that is used to disconnect the switched power area from a power supply pad; and
a selection unit that includes a first input for receiving signals from a source external to the circuit, a second input for receiving signals from the inactive state power reduction manager, a control input for receiving a save-state mode signal, and an output that is coupled to the scan circuitry;
wherein the inactive state power reduction manager performs a scan-based state-save by generating the save-state mode signal and by providing signals to the second input of the selection unit.
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Abstract
A scan-based state save and restore method and system for inactive state power reduction. An integrated circuit that has an inactive state has normal circuitry and scan circuitry. Upon receipt of a sleep signal, the state of the normal circuitry is accessed by employing scan circuitry. The state is then stored in a memory. The power is disconnected from the normal circuitry. Upon wake-up, the normal circuitry is re-connected to the power. The state of the circuit is accessed from the memory and restored to the normal circuitry by employing scan circuitry.
58 Citations
20 Claims
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1. A circuit having scan circuitry comprising:
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a constant power area that receives constant power; a switched power area that receives interruptible power;
wherein the switched power area includes an input for receiving a normal mode clock signal; andan inactive state power reduction manager disposed in the constant power area for receiving a sleep signal and responsive thereto for asserting a stop clock signal to stop the normal mode clock, for performing a scan-based state-save by employing the scan circuitry, and for asserting a power control signal that is used to disconnect the switched power area from a power supply pad; and a selection unit that includes a first input for receiving signals from a source external to the circuit, a second input for receiving signals from the inactive state power reduction manager, a control input for receiving a save-state mode signal, and an output that is coupled to the scan circuitry;
wherein the inactive state power reduction manager performs a scan-based state-save by generating the save-state mode signal and by providing signals to the second input of the selection unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for inactive state power reduction for a circuit that has scan circuitry and a switched power portion;
- wherein the switched power portion includes an input for receiving a normal mode clock signal, the method comprising;
receiving a sleep signal; responsive to the sleep signal, stopping the normal mode clock; performing a state save by employing the scan circuitry and a selection unit that includes a first input for receiving signals from a source external to the circuit, a second input for receiving signals from an inactive state power reduction manager, a control input for receiving a save-state mode signal, and an output that is coupled to the scan circuitry; and d) disconnecting the switched power portion of the circuit from power. - View Dependent Claims (15, 16)
- wherein the switched power portion includes an input for receiving a normal mode clock signal, the method comprising;
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17. A circuit board comprising:
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a first integrated circuit having a test access port;
an input for receiving a normal mode clock signal;a second integrated circuit having a test access port ;
an input for receiving the normal mode clock signal; andan inactive state power reduction manager coupled to the first integrated circuit and the second integrated circuit for receiving a sleep signal and responsive thereto for asserting a stop clock signal to stop the normal mode clock, for performing a scan-based state save of state information of the first integrated circuit and the second integrated circuit by using the test access port of the first integrated circuit and the second integrated circuit, respectively, and for asserting a power control signal that is used to disconnect the first integrated circuit and the second integrated circuit from a power supply; and a selection unit that includes a first input for receiving signals from a source external to the circuit, a second input for receiving signals from the inactive state power reduction manager, a control input for receiving a save-state mode signal from the inactive state power reduction manager, and an output that is coupled to the test access port. - View Dependent Claims (18, 19, 20)
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Specification