Selecting different 1149.1 TAP domains from update-IR state

• US 7,058,862 B2
• Filed: 05/24/2001
• Issued: 06/06/2006
• Est. Priority Date: 05/26/2000
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D., Haroun, Baher S., Lasher, Brian J., Kinra, Anjali
• Primary Examiner(s): Lamarre, Guy
• Assistant Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US09/864,509
• Publication Number:
  US 20020049928A1
• Time in Patent Office: 1,839 Days
• Field of Search: 714/724, 714/726, 714/727, 714/733, 714 27- 30, 326/16
• US Class Current: 714/30
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318555 Control logic

Abstract

IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Claims

1. A process of selecting different 1149.1 TAP domain arrangements within an integrated circuit comprising:

A. performing an 1149.1 instruction shift operation through a first 1149.1 TAP domain arrangement;

B. performing an 1149.1 instruction update operation at the end of the 1149.1 instruction shift operation; and

C. in response to said 1149.1 instruction update operation, selecting a second 1149.1 TAP domain arrangement that differs from the first 1149.1 TAP domain arrangement.

2. The process of claim 1 including performing the 1149.1 instruction shift operation in accordance with the 1149.1 IEEE Standard titled Test Access Port and Boundary-Scan Architecture.

3. The process of claim 1 including performing the 1149.1 instruction update operation in accordance with the 1149.1 IEEE Standard titled Test Access Port and Boundary-Scan Architecture.

4. The process of claim 1 including performing a select DR operation, a select IR operation, and a capture IR operation before performing the instruction shift operation.

5. The process of claim 1 including performing one of a select DR operation and a Run Test/Idle operation after performing the instruction update operation.