Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits

• US 7,058,869 B2
• Filed: 01/23/2004
• Issued: 06/06/2006
• Est. Priority Date: 01/28/2003
• Status: Expired due to Fees

• Current Assignee: Syntest Technologies Incorporated
• Original Assignee: Syntest Technologies Incorporated
• Inventors: Abdel-Hafez, Khader S., Wang, Hsin-Po, Wang, Laung-Terng, Wen, Xiaoqing, Kao, Shih-Chia, Chao, Hao-Jan, Hsu, Po-Ching
• Primary Examiner(s): DILDINE JR, R STEPHEN
• Application Number:
  US10/762,571
• Publication Number:
  US 20040237015A1
• Time in Patent Office: 865 Days
• Field of Search: 714/727, 714/729
• US Class Current: 714/729
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G01R 31/318591 Tools

Abstract

A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core 303 have no external access, such as the case when they are surrounded by pattern generators 302 and pattern compactors 305, using a DFT (design-for-test) technology such as Logic BIST (built-in self-test) or Compressed Scan. This invention includes an output-mask controller 301 and an output-mask network 304 to allow designers to mask off selected scan cells 311 from being compacted in a selected pattern compactor 305. This invention also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations. Computer-aided design (CAD) methods are then proposed to automatically synthesize the output-mask controller 301, output-mask network 304, input chain-mask controller and input-mask network, and to further generate test patterns according to the synthesized scan-based integrated circuit.

Claims

1. A method for selectively masking off undesirable states in selected scan cells, which cause test failures, from being compacted in selected pattern compactors for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, an output-mask controller, and an output-mask network, each scan chain comprising multiple scan cells coupled in series, the output-mask controller including a combinational output controller connected to the output-mask network, the combinational output controller comprising one or more selected combinational logic networks other than a complete network of AND gates;

said method comprising;

(a) generating and shifting in a stimulus through said pattern generators to all said scan cells in said scan-based integrated circuit during a shift-in operation;

said generating and shifting in a stimulus through said pattern generators to all said scan cells further comprises generating a compressed stimulus, decompressing said compressed stimulus as said stimulus through said pattern generators, and shifting in said stimulus to all said scan cells in said selected scan-test mode during said shift-in operation;

wherein said compressed stimulus is selectively generated internally or supplied externally from an ATE (automatic test equipment);

(b) capturing a test response to all said scan cells during a selected capture operation;

(c) shifting out said test response or said stimulus to said pattern compactors for compaction by selectively masking off said undesirable states in said selected scan cells from being compacted in said selected pattern compactors using said output-mask controller and said output-mask network, while shifting in a new stimulus to all said scan cells, during a shift-out operation; and

(d) repeating steps (b) to (c) until a predetermined limiting criteria is reached.

2. The method of claim 1, wherein each said pattern generator is selectively a broadcaster or a decompressor.

3. A method for selectively masking off undesirable states in selected scan cells, which cause test failures, from being compacted in selected pattern compactors for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, an output-mask controller, and an output-mask network, each scan chain comprising multiple scan cells coupled in series, the output-mask controller including a combinational output controller connected to the output-mask network, the combinational output controller comprising one or more selected combinational logic networks other than a complete network of AND gates;

said method comprising;

(a) generating and shifting in a stimulus through said pattern generators to all said scan cells in said scan-based integrated circuit during a shift-in operation;

said generating and shifting in a stimulus through said pattern generators to all said scan cells further comprises using a load signal to preset said output-mask controller with a predetermined state for selectively masking off said undesirable states in said selected scan cells from being compacted in said selected pattern compactors during a selected shifting operation;

(b) capturing a test response to all said scan cells during a selected capture operation;

(c) shifting out said test response or said stimulus to said pattern compactors for compaction by selectively masking off said undesirable states in said selected scan cells from being compacted in said selected pattern compactors using said output-mask controller and said output-mask network, while shifting in a new stimulus to all said scan cells, during a shift-out operation; and

(d) repeating steps (b) to (c) until a predetermined limiting criteria is reached.

4. A method for selectively masking off undesirable states in selected scan cells, which cause test failures, from being compacted in selected pattern compactors for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, an output-mask controller, and an output-mask network, each scan chain comprising multiple scan cells coupled in series, the output-mask controller including a combinational output controller connected to the output-mask network, the combinational output controller comprising one or more selected combinational logic networks other than a complete network of AND gates;

said method comprising;

(a) generating and shifting in a stimulus through said pattern generators to all said scan cells in said scan-based integrated circuit during a shift-in operation;

said shifting out said test response or said stimulus to said pattern compactors for compaction further comprises using said output-mask controller to generate a plurality of output-mask enable signals for controlling said output-mask network for selectively mask off said undesirable states in said selected scan cells from being compacted in said selected pattern compactors during said shift-out operation;

said output-mask controller further comprises a sequential output controller for generating a plurality of sequential-mask signals and said combinational output controller for generating said output-mask enable signals;

(b) capturing a test response to all said scan cells during a selected capture operation;

(c) shifting out said test response or said stimulus to said pattern compactors for compaction by selectively masking off said undesirable states in said selected scan cells from being compacted in said selected pattern compactors using said output-mask controller and said output-mask network, while shifting in a new stimulus to all said scan cells, during a shift-out operation; and

(d) repeating steps (b) to (c) until a predetermined limiting criteria is reached.

5. The method of claim 4, wherein said sequential output controller in said output-mask controller further comprises a plurality of selected cell-mask controllers for generating one or more selected cell-mask signals, a plurality of selected chain-mask controllers for generating one or more selected chain-mask signals, and a plurality of selected pattern-mask controllers for generating one or more selected pattern-mask signals;

wherein said selected cell-mask signals, said selected chain-mask signals, and said selected pattern-mask signals are collectively referred to as said sequential-mask signals.

6. The method of claim 5, wherein each said cell-mask controller in said sequential output controller is a first finite-state machine generating one or more said selected cell-mask signals.

7. The method of claim 6, wherein said first finite-state machine is selectively a ring counter (RC) or a first range comparator.

8. The method of claim 5, wherein each said chain-mask controller in said sequential output controller is a second finite-state machine generating one or more said selected chain-mask signals.

9. The method of claim 8, wherein said second finite-state machine is selectively a first shift register (SR) or a range decoder.

10. The method of claim 5, wherein each said pattern-mask controller in said sequential output controller is a third finite-state machine generating one or more said selected pattern-mask signals.

11. The method of claim 10, wherein said third finite-state machine is selectively a second shift register (SR) or a second range comparator.

12. The method of claim 4, wherein said combinational output controller, comprising one or more said selected combinational logic networks other than said complete network of AND gates, further accepts said sequential-mask signals as inputs for generating said output-mask enable signals for controlling said output-mask network for selectively masking off all said undesirable states in said selected scan cells from being compacted in said selected pattern compactors during said shift-out operation.

13. The method of claim 12, wherein each said selected combinational logic network further comprises one or more first selected combinational gates;

wherein each said first selected combinational gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), or inverter (INV).

14. A method for selectively masking off undesirable states in selected scan cells, which cause test failures, from being compacted in selected pattern compactors for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, an output-mask controller, and an output-mask network, each scan chain comprising multiple scan cells coupled in series, the output-mask controller including a combinational output controller connected to the output-mask network, the combinational output controller comprising one or more selected combinational logic networks other than a complete network of AND gates;

said method comprising;

(a) generating and shifting in a stimulus through said pattern generators to all said scan cells in said scan-based integrated circuit during a shift-in operation;

each said pattern compactor is selectively a multi-input signature register (MISR) or a linear compactor;

wherein said linear compactor further includes one or more third selected combinational gates;

wherein each said third selected combinational gate is selectively an Exclusive-OR (XOR) gate or Exclusive-NOR (XNOR) gate;

(b) capturing a test response to all said scan cells during a selected capture operation;

(c) shifting out said test response or said stimulus to said pattern compactors for compaction by selectively masking off said undesirable states in said selected scan cells from being compacted in said selected pattern compactors using said output-mask controller and said output-mask network, while shifting in a new stimulus to all said scan cells, during a shift-out operation; and

(d) repeating steps (b) to (c) until a predetermined limiting criteria is reached.

15. An output-mask controller for generating a plurality of output-mask enable signals for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, and an output-mask network, each scan chain comprising multiple scan cells coupled in series;

said output-mask controller comprising;

(a) a sequential output controller for generating a plurality of sequential-mask signals;

wherein said sequential output controller further comprises a plurality of selected cell-mask controllers for generating one or more selected cell-mask signals, a plurality of selected chain-mask controllers for generating one or more selected chain-mask signals, and a plurality of selected pattern-mask controllers for generating one or more selected pattern-mask signals;

wherein said selected cell-mask signals, said selected chain-mask signals, and said selected pattern-mask signals are collectively referred to as said sequential-mask signals; and

(b) a combinational output controller, comprising one or more selected combinational logic networks other than a complete network of AND gates, for generating a plurality of output-mask enable signals for controlling said output-mask network for selectively masking off undesirable states in selected scan cells, which cause test failure, from being compacted in selected pattern compactors.

16. The output-mask controller of claim 15, wherein each said cell-mask controller in said sequential output controller is a first finite-state machine generating one or more said selected cell-mask signals.

17. The output-mask controller of claim 16, wherein said first finite-state machine is selectively a ring counter (RC) or a first range comparator.

18. The output-mask controller of claim 15, wherein each said chain-mask controller in said sequential output controller is a second finite-state machine generating one or more selected chain-mask signals.

19. The output-mask controller of claim 18, wherein said second finite-state machine is selectively a first shift register (SR) or a range decoder.

20. The output-mask controller of claim 15, wherein each said pattern-mask controller in said sequential output controller is a third finite-state machine generating one or more said selected pattern-mask signals.

21. The output-mask controller of claim 20, wherein said third finite-state machine is second shift register (SR) or a second range comparator.

22. An output-mask controller for generating a plurality of output-mask enable signals for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, and an output-mask network, each scan chain comprising multiple scan cells coupled in series;

said output-mask controller comprising;

(a) a sequential output controller for generating a plurality of sequential-mask signals;

wherein said combinational output controller, comprising one or more said selected combinational logic networks other than said complete network of AND gates, further accepts said sequential-mask signals as inputs for generating said output-mask enable signals for controlling said output-mask network for selectively masking off said undesirable states in said selected scan cells from being compacted in said selected pattern compactors; and

(b) a combinational output controller, comprising one or more selected combinational logic networks other than a complete network of AND gates, for generating a plurality of output-mask enable signals for controlling said output-mask network for selectively masking off undesirable states in selected scan cells, which cause test failure, from being compacted in selected pattern compactors.

23. The output-mask controller of claim 22, wherein each said selected combinational logic network further comprises one or more first selected combinational gates;

wherein each said first selected combinational gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), or inverter (INV).

24. A method for selectively driving selected constant logic values into all scan cells in selected scan chains for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, an input chain-mask controller, and an input-mask network, each scan chain comprising multiple scan cells coupled in series, the input chain-mask controller connected to the input-mask network;

said method comprising;

(a) generating and shifting in a stimulus through said pattern generators to all said scan cells in said scan-based integrated circuit by selectively forcing said selected constant logic values into all said scan cells in said selected scan chains during a shift-in operation;

said generating and shifting in a stimulus through said pattern generators to all said scan cells further comprises generating a compressed stimulus, decompressing said compressed stimulus as said stimulus through said pattern generators, and shifting in said stimulus to all said scan cells in said selected scan-test mode during said shift-in operation;

wherein said compressed stimulus is selectively generated internally or supplied externally from an ATE (automatic test equipment);

(b) capturing a test response to all said scan cells during a selected capture operation;

(c) shifting out said test response or said stimulus to said pattern compactors for compaction, while shifting in a new stimulus to all said scan cells in said scan-based integrated circuit, during a shift-out operation; and

(d) repeating steps (b) to (c) until a predetermined limiting criteria is reached.

25. The method of claim 24, wherein each said pattern generator is selectively a broadcaster or a decompressor.

26. A method for selectively driving selected constant logic values into all scan cells in selected scan chains for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, an input chain-mask controller, and an input-mask network, each scan chain comprising multiple scan cells coupled in series, the input chain-mask controller connected to the input-mask network;

said method comprising;

(a) generating and shifting in a stimulus through said pattern generators to all said scan cells in said scan-based integrated circuit by selectively forcing said selected constant logic values into all said scan cells in said selected scan chains during a shift-in operation;

wherein said generating and shifting in a stimulus through said pattern generators to all said scan cells further comprises automatically generating said stimulus internally using said pattern generators in said selected self-test mode during said shift-in operation;

wherein each said pattern generator is selectively a pseudorandom pattern generator (PRPG) or a random pattern generator (RPG);

(b) capturing a test response to all said scan cells during a selected capture operation;

(c) shifting out said test response or said stimulus to said pattern compactors for compaction, while shifting in a new stimulus to all said scan cells in said scan-based integrated circuit, during a shift-out operation; and

(d) repeating steps (b) to (c) until a predetermined limiting criteria is reached.

27. The method of claim 26, wherein said generating and shifting in a stimulus through said pattern generators to all said scan cells further comprises using a load signal to preset said input chain-mask controller with a predetermined state to selectively force said selected constant logic values into all said scan cells in said selected scan chains during a selected shift-in operation.

28. The method of claim 26, wherein said generating and shifting in a stimulus through said pattern generators to all said scan cells further comprises using said input chain-mask controller to generate a plurality of input-mask enable signals for controlling said input-mask network to selectively force said selected constant logic values into all said scan cells in said selected scan chains during said shift-in operation.

29. The method of claim 28, wherein said input chain-mask controller further comprises using an initialize signal to prevent said input-mask enable signals from forcing said selected constant logic values into all said scan cells in said selected scan chains.

30. The method of claim 28, wherein said input chain-mask controller is a finite-state machine generating said input-mask enable signals.

31. The method of claim 30, wherein said finite-state machine is selectively a shift register (SR) or a range decoder.

32. A method for selectively driving selected constant logic values into all scan cells in selected scan chains for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, an input chain-mask controller, and an input-mask network, each scan chain comprising multiple scan cells coupled in series, the input chain-mask controller connected to the input-mask network;

said method comprising;

(a) generating and shifting in a stimulus through said pattern generators to all said scan cells in said scan-based integrated circuit by selectively forcing said selected constant logic values into all said scan cells in said selected scan chains during a shift-in operation;

wherein each said pattern compactor is selectively a multi-input signature register (MISR) or a linear compactor;

wherein said linear compactor further includes one or more second selected combinational gates;

wherein each said second selected combinational gate is selectively an Exclusive-OR (XOR) gate or Exclusive-NOR (XNOR) gate;

(b) capturing a test response to all said scan cells during a selected capture operation;

(c) shifting out said test response or said stimulus to said pattern compactors for compaction, while shifting in a new stimulus to all said scan cells in said scan-based integrated circuit, during a shift-out operation; and

(d) repeating steps (b) to (c) until a predetermined limiting criteria is reached.

33. An input chain-mask controller for generating a plurality of input-mask enable signals for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, and an input-mask network, each scan chain comprising multiple scan cells coupled in series;

said input chain-mask controller comprising;

a finite-state machine for generating said input-mask enable signals for controlling said input-mask network to selectively force selected constant logic values into all scan cells in selected scan chains, and wherein said finite-state machine further comprises using a load signal to preset said input chain-mask controller with a predetermined state to selectively force said selected constant logic values into all said scan cells in said selected scan chains.

34. An input chain-mask controller for generating a plurality of input-mask enable signals for debug, diagnosis, and/or yield improvement of a scanbased integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, and an input-mask network, each scan chain comprising multiple scan cells coupled in series;

said input chain-mask controller comprising;

a finite-state machine for generating said input-mask enable signals for controlling said input-mask network to selectively force selected constant logic values into all scan cells in selected scan chains; and

wherein said finite-state machine is selectively a shift register (SR) or a range decoder.