Distributed 4-bits diagonal interleaved parity (DIP4) checker

• US 7,058,881 B2
• Filed: 09/05/2002
• Issued: 06/06/2006
• Est. Priority Date: 03/15/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Chu, Ngok Ying
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US10/234,165
• Publication Number:
  US 20030182613A1
• Time in Patent Office: 1,370 Days
• Field of Search: 714/807, 714/758, 714/775, 714/781, 714/798
• US Class Current: 714/807
• CPC Class Codes: H03M 13/33 Synchronisation based on error coding or decoding
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/008 where the control data relates to payload of a different packet

Abstract

A logic circuit includes an interface and an error detection unit. The interface is configured to receive and transmit a data stream, wherein the data stream includes at least one of a variable length format packet or burst and a fixed length format packet or burst. The error detection unit is configured to detect an error detection code error when a misalignment occurs within the data stream by recursively calculating parity terms.

Claims

1. A logic circuit comprising:

an interface configured to receive and transmit a data stream; and

an error detection unit configured to detect an error detection code error when a misalignment occurs within said data stream by recursively calculating parity terms, wherein the data stream comprises at least one of a variable length burst and a fixed length burst and said error detection unit is configured to perform error detection on said data stream comprising a 64-bit input data bus and a 4-bit control bus.

2. The logic circuit as recited in claim 1, wherein said error detection unit is configured to assign said data stream to columns and rows within a parity calculation staging matrix;

wherein said parity calculation staging matrix is configured to determine at least one parity bit within said data stream; and

wherein said parity bit is configured to detect an error within said data stream.

3. The logic circuit as recited in claim 2, wherein said error detection unit recursively calculates the parity terms according to the equations:

P(3)=D(3)^C(0)^B(1)^A(2)

P(2)=D(2)^C(3)^B(0)^A(1)

P(1)=D(1)^C(2)^B(3)^A(0)

P(0)=D(0)^C(1)^B(2)^A(3)

where the “

P-terms”

are the parity terms and comprise four bits and where “

A”

, “

B”

, “

C”

, and “

D”

are variables representing a 16-bit input calculated by said logic circuit.

4. The logic circuit as recited in claim 3, wherein said error detection unit calculates an intermediate term to determine a feedback loop value used to determine a next parity bit.

5. The logic circuit as recited in claim 4, wherein said error detection unit utilizes said intermediate term to determine said recursive terms input into said feedback loop to calculate said next parity bit.

6. The logic circuit as recited in claim 5, wherein said error detection unit utilizes a previous parity bit as a feedback loop value to determine a next intermediate term parity bit.

7. The logic circuit as recited in claim 6, wherein said error detection unit is configured to generate a bit map having at least two data fields, wherein said bit map is configured to indicate a location within said data stream to check for said parity bit.

8. The logic circuit as recited in claim 7, wherein said bit map includes a mask configured to detect a classification of a current input of said data stream and a previous input of said data stream;

and

wherein said bit map determines said next intermediate term parity bit based upon said classification of the current input and a previous input.

9. The logic circuit as recited in claim 8, wherein said error detection unit utilizes said previous parity bit and said current input to determine said next intermediate term parity bit based upon a first data classification and a second data classification.

10. The logic circuit as recited in claim 9, wherein said data stream comprises variable length bursts.

11. A method of error detection within a logic circuit, said method comprising:

interfacing a first device having a first transfer rate with a second device having a second transfer rate;

receiving a data stream;

calculating a parity bit within said data stream;

calculating an intermediate term to determine a feedback loop value used to determine a next intermediate term parity bit;

detecting an error detection code to detect an error within said data stream; and

recursively calculating parity terms.

12. The method as recited in claim 11, further comprising the step of:

filling a parity calculation staging matrix.

13. The method as recited in claim 12, further comprising the step of:

recursively calculating the parity terms according to the equations;

P(3)=D(3)^C(0)^B(1)^A(2)

P(2)=D(2)^C(3)^B(0)^A(1)

P(1)=D(1)^C(2)^B(3)^A(0)

P(0)=D(0)^C(1)^B(2)^A(3)

where the “

P-terms”

are the parity terms and comprise four bits and where “

A”

“

B”

, “

C” and

“

D”

are variables terms representing a 16-bit input calculated by said logic circuit.

14. The method as recited in claim 13, further comprising the step of:

utilizing said intermediate term to determine said recursively calculated parity terms input into said feedback loop to calculate said next parity bit.

15. The method as recited in claim 14, further comprising the step of:

receiving variable length bursts into said interface.

16. A logic circuit comprising:

an interface means for receiving and transmitting a data stream; and

an error detection means for detecting an error detection code error by recursively calculating a parity term, wherein the data stream comprises at least one of a variable length burst or a fixed length burst and said error detection means is configured to perform error detection on said data stream comprising a 64-bit input data bus and a 4-bit control bus.

17. The logic circuit as recited in claim 16, wherein said error detection means recursively calculates the parity terms according to the equations:

P(3)=D(3)^C(0)^B(1)^A(2)

P(2)=D(2)^C(3)^B(0)^A(1)

P(1)=D(1)^C(2)^B(3)^A(0)

P(0)=D(0)^C(1)^B(2)^A(3)

where the “

P-terms”

are the parity terms and comprise four bits and where “

A”

, “

B”

, “

C”

, and “

D”

are variables terms representing a 16-bit input calculated by said logic circuit.

18. The logic circuit as recited in claim 17, wherein said error detection means calculates an intermediate term to determine a feedback loop value used to determine a next parity bit.

19. The logic circuit as recited in claim 18, wherein said error detection means utilizes said intermediate term to determine said recursively calculated parity terms input into said feedback loop to calculate said next parity bit.

20. The logic circuit as recited in claim 19, wherein said error detection means utilizes a previous parity bit as a feedback loop value to determine a next intermediate term parity bit.