Semiconductor integrated circuit and method of manufacturing the same

• US 7,058,922 B2
• Filed: 04/28/2005
• Issued: 06/06/2006
• Est. Priority Date: 07/13/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawanaka, Shigeru
• Primary Examiner(s): Lin, Sun James
• Application Number:
  US11/116,298
• Publication Number:
  US 20050185440A1
• Time in Patent Office: 404 Days
• Field of Search: 716/18, 716/1, 327/81, 257/347, 257/350, 257/351
• US Class Current: 716/54
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage-activated transistors which have the same channel conduction type and are electrically connected in series between a power supply terminal and an output terminal. A source region and a body region of at least the voltage-activated transistor connected to the output terminal are electrically connected and have substantially the same potential. The semiconductor integrated circuit has either an SOI or SOS structure.

Claims

1. A method of manufacturing a semiconductor integrated circuit comprising:

forming a plurality of voltage-activated transistors in a semiconductor layer on a substrate having an insulator at least on a surface thereof, said plurality of voltage-activated transistors including body contact regions electrically connectable one of body regions being electrically isolated from each other and being electrically isolated from said substrate and a source region and having the same channel conduction type; and

electrically connecting said plurality of voltage-activated transistors in series to a power supply terminal and an output terminal, and to said source region and said body contact region of at least one of said plurality of voltage-activated transistors near said output terminal, a drain region and a gate electrode of at least one of said voltage-activated transistors near said output terminal being not electrically connected.