Multi-package stack module

• US 7,061,087 B2
• Filed: 10/02/2003
• Issued: 06/13/2006
• Est. Priority Date: 10/24/2002
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jin-Ho
• Primary Examiner(s): Vigushin, John B.
• Application Number:
  US10/678,412
• Publication Number:
  US 20040090759A1
• Time in Patent Office: 985 Days
• Field of Search: None
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate

Abstract

A multi-package module comprises a plurality of stacked packages including an upper package and a lower package. Each package comprises a board having located on a first side thereof a chip installation area and a bump pad area; at least one chip disposed in the chip installation area; a plurality of redistribution patterns formed on the board and electrically connected to the chip; and a plurality of first bump pads formed in the bump pad area which are electrically connected to the redistribution patterns. The respective packages are electrically connected by connecting bump pads of the upper package to bump pads of the lower package. Further, the chip installation area of the upper and lower packages not being in vertical alignment with each other.

Claims

1. A multi-package module comprising a plurality of stacked packages including an upper package and a lower package, each package comprising:

a board having located on one side thereof a chip installation area and a bump pad area;

at least one chip disposed in the chip installation area; and

a plurality of first bump pads formed in the bump pad area electrically connected to the chip,

wherein the respective packages are electrically connected by connecting bump pads of the upper package to bump pads of the lower package, the chip installation area of the upper and lower packages being laterally offset from each other, wherein a plurality of second bump pads are formed on a second side of the board, and a plurality of via holes through which the second bump pads are electrically connected to redistribution patterns, and wherein the second bump pads are formed on the second side of the board in the space corresponding to the chip installation area on the first side of the board.

2. A multi-package module comprising a plurality of stacked packages including an upper package and a lower package,

each package comprising:

a board having located on a first side thereof a chip installation area and a bump pad area;

at least one chip disposed in the chip installation area;

a plurality of redistribution patterns formed on the board and electrically connected to the chip;

a plurality of first bump pads formed in the bump pad area which are electrically connected to the redistribution patterns;

a plurality of second bump pads formed on a second side of the board; and

a plurality of via holes through which the second bump pads are electrically connected to the redistribution patterns,

wherein the respective packages are electrically connected by connecting the second bump pads of the upper of two adjacent packages to the first bump pads of the lower package, the chip installation area of the upper and lower packages not being in vertical alignment with each other, the chip installation area being positioned on about one half of the first side of the board, and the bump pad area being positioned on about the other one half of the first side of the board.

3. A multi-package module according to claim 2, wherein the second bump pads are formed on the second side of the board in the space corresponding to the chip installation area on the first side of the board.

4. A multi-package module according to claim 2, wherein conductive bumps are provided on the second bump pads for electrically connecting the second bump pads of the upper of two adjacent packages to the first bump pads of the lower package.

5. A multi-package module according to claim 4, wherein a portion of the conductive bumps of any two adjacent packages are not in vertical alignment with each other.

6. A multi-package module according to claim 2, which further includes an encapsulation member surrounding the chip for protecting the chip from the external environment.

7. A multi-package module according to claim 6, wherein conductive bumps are provided having similar heights to the height of the encapsulation member.

8. A multi-package module according to claim 2, wherein the second bump pads are formed on substantially the entire second side of the board of the lower package.

9. A multi-package module according to claim 2, further comprising at least one electronic device is disposed on the board of the upper package, and electrically connected to the first bump pads of the upper package.

10. A multi-package module comprising a plurality of stacked packages including an upper package and a lower package, each package comprising:

a board having located on a first side thereof a chip installation area and a bump pad area;

at least one chip disposed in the chip installation area;

a plurality of redistribution patterns formed on the board and electrically connected to the chip; and

a plurality of first bump pads formed in the bump pad area which are electrically connected to the redistribution patterns,

wherein the respective packages are electrically connected by connecting bump pads of the upper package to bump pads of the lower package, the chip installation area of the upper and lower packages not being in vertical alignment with each other, wherein a plurality of second bump pads are formed on a second side of the board, and a plurality of via holes through which the second bump pads are electrically connected to the redistribution patterns,

and wherein the second bump pads are formed on the second side of the board in the space corresponding to the chip installation area on the first side of the board.

11. A multi-package module according to claim 10, which further includes an encapsulation member surrounding the chip for protecting the chip from the external environment.

12. A multi-package module according to claim 11, wherein conductive bumps are provided having similar heights to the height of the encapsulation member.

13. A multi-package module according to claim 10, wherein the chip installation area is positioned on about one half of the first side of the board, and the bump pad area is positioned on about the other one half of the first side of the board.

14. A multi-package module according to claim 10, wherein at least one electronic device is disposed on the board of the upper package, and is electrically connected to the first bump pads of the upper package.

15. A multi-package module according to claim 10, wherein the packages are electrically connected by connecting the second bump pads of the upper of two adjacent packages to the first bump pads of the lower package.

16. A multi-package module according to claim 10, wherein conductive bumps are provided on the second bump pads for electrically connecting the second bump pads of the upper package to the first bump pads of the lower package.

17. A multi-package module according to claim 10, wherein the second bump pads are formed on substantially the entire second side of the board of the lower package.