System and method for high frequency, high output swing buffers

• US 7,061,279 B1
• Filed: 12/30/2004
• Issued: 06/13/2006
• Est. Priority Date: 12/30/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Leete, John
• Primary Examiner(s): Nguyen, Long
• Assistant Examiner(s): Jager, Ryan
• Application Number:
  US11/026,372
• Publication Number:
  US 20060145728A1
• Time in Patent Office: 530 Days
• Field of Search: 327108-112, 327/560, 327/563, 330252-255, 330/261, 330/277, 330/301, 330/302, 326 82- 92, 360/46, 360/67, 360/68, 363/58, 363/63
• US Class Current: 327/65
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2203/45008 the addition of two signals being made by a resistor addition circuit for producing the common mode signal
• CPC Class Codes: H03F 2203/45248 the dif amp being designed for improving the slew rate
• CPC Class Codes: H03F 2203/45316 the AAC comprising one or more discrete inductive elements or coils
• CPC Class Codes: H03F 2203/45528 the FBC comprising one or more passive resistors and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45544 the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/45735 Controlling the active amplifying circuit of the differential amplifier
• CPC Class Codes: H03K 19/018578 with at least one differential stage
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/103 the additional signal being a digital signal
• CPC Class Codes: H03L 7/1978 using a cycle or pulse removing circuit

Abstract

Methods and systems for increasing gain for an electric circuit may include receiving an input differential signal at a first configured pair of transistors and a second configured pair of transistors. The first and second configured pair of transistors may be inductively loaded. The first configured pair of transistors may be self-biased via the inductive loading. DC current may be generated via the second configured pair of transistors. The first and/or the second configured pair of transistors may be configured as input transconductors. A pair of inductors may be configured for the inductive loading and the configured pair of inductors may be tapped for the self-biasing. If the first configured pair of transistors comprises NMOS transistors, then the second configured pair of transistors may comprise PMOS transistors.

Claims

1. A method for increasing output gain of an electronic circuit, the method comprising:

receiving an input differential signal at a first pair of transistors and a second pair of transistors;

inductively loading said first pair of transistors and said second pair of transistors;

self-biasing said first pair of transistors via said inductive loading; and

generating DC current via said second pair of transistors,

wherein said inductive loading is performed by an inductive load directly coupled to said first pair of transistors and said second pair of transistors.

2. The method according to claim 1, further comprising configuring said first pair of transistors as input transconductors.

3. The method according to claim 1, further comprising configuring said second pair of transistors as input transconductors.

4. The method according to claim 1, further comprising configuring a pair of inductors for said inductive loading.

5. The method according to claim 4, further comprising tapping said configured pair of inductors for said self-biasing.

6. The method according to claim 1, wherein when said first pair of transistors comprises NMOS transistors, then said second pair of transistors are PMOS transistors.

7. The method according to claim 1, wherein when said first pair of transistors comprises PMOS transistors, then said second pair of transistors are NMOS transistors.

8. An apparatus for increasing output gain of an electronic circuit, the apparatus comprising:

a first pair of transistors and a second pair of transistors that each receives an input differential signal;

an inductive load that inductively loads said first pair of transistors and said second pair of transistors;

said inductive load self-biases said first pair of transistors; and

said second pair of transistors generates DC current,

wherein said inductive load is directly coupled to said first pair of transistors and said second pair of transistors.

9. The apparatus according to claim 8, wherein said first pair of transistors is configured as input transconductors.

10. The apparatus according to claim 8, wherein said second pair of transistors is configured as input transconductors.

11. The apparatus according to claim 8, wherein said inductive load further comprises a pair of inductors for said inductive loading.

12. The apparatus according to claim 11, further comprising a tap that taps said configured pair of inductors for said self-biasing.

13. The apparatus according to claim 8, wherein said second pair of transistors are PMOS transistors, when said first pair of transistors comprises NMOS transistors.

14. The apparatus according to claim 8, wherein said second pair of transistors are NMOS transistors, when said first pair of transistors comprises PMOS transistors.

15. An apparatus for increasing gain for an electric circuit, the apparatus comprising:

a first transistor, wherein a gate of said first transistor is coupled to a first differential input;

a second transistor, wherein a gate of said second transistor is coupled to a second differential input;

a third transistor, wherein a gate of said third transistor is coupled to said first differential input; and

a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein;

said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;

said DC voltage source is coupled to said third transistor and said fourth transistor; and

said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor.

16. The apparatus according to claim 15, wherein said first transistor and said second transistor comprise NMOS transistors.

17. The apparatus according to claim 15, wherein said first transistor and said second transistor comprise PMOS transistors.

18. The apparatus according to claim 15, wherein said third transistor and said fourth transistor comprise PMOS transistors, when said first transistor and said second transistor comprise NMOS transistors.

19. The apparatus according to claim 15, wherein said third transistor and said fourth transistor comprise NMOS transistors, when said first transistor and said second transistor comprise PMOS transistors.

20. The apparatus according to claim 15, further comprising a load inductor coupled to said DC voltage source.

21. The apparatus according to claim 15, wherein a first terminal of a first resistor is coupled to said gate of said first transistor.

22. The apparatus according to claim 21, wherein a second terminal of said first resistor is coupled to said common mode output of said DC voltage source.

23. The apparatus according to claim 15, wherein a first terminal of a second resistor is coupled to said gate of said second transistor.

24. The apparatus according to claim 23, wherein a second terminal of said second resistor is coupled to said common mode output of said DC voltage source.

25. The apparatus according to claim 15, wherein a first terminal of a load inductor is coupled to a drain of said first transistor and a drain of said third transistor.

26. The apparatus according to claim 15, wherein a second terminal of a load inductor is coupled to a drain of said second transistor and a drain of said fourth transistor.

27. The apparatus according to claim 15, wherein said gate of said first transistor is coupled to a first capacitor.

28. The apparatus according to claim 15, wherein said gate of said second transistor is coupled to a second capacitor.

29. The apparatus according to claim 15, wherein said gate of said third transistor is coupled to a third capacitor.

30. The apparatus according to claim 15, wherein said gate of said fourth transistor is coupled to a fourth capacitor.

31. The apparatus according to claim 15, wherein a source of said first transistor and a source of said second transistor are coupled to ground.

32. An apparatus for increasing gain for an electric circuit, the apparatus comprising:

a first transistor, wherein a gate of said first transistor is coupled to a first differential input;

a second transistor, wherein a gate of said second transistor is coupled to a second differential input;

a third transistor, wherein a gate of said third transistor is coupled to said first differential input; and

a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein;

said third transistor and said fourth transistor are biased by a common mode output of a direct current (DC) voltage source;

said DC voltage source is coupled to said third transistor and said fourth transistor; and

said common mode output of said DC voltage source is coupled to said gate of said third transistor and said gate of said fourth transistor.

33. A method for increasing output gain of an electronic circuit, the method comprising:

receiving an input differential signal at a first pair of transistors and a second pair of transistors;

inductively loading said first pair of transistors and said second pair of transistors;

self-biasing said first pair of transistors via said inductive loading; and

generating DC current via said second pair of transistors,

wherein when said first pair of transistors comprises NMOS transistors, then said second pair of transistors are PMOS transistors.

34. A method for increasing output gain of an electronic circuit, the method comprising:

receiving an input differential signal at a first pair of transistors and a second pair of transistors;

inductively loading said first pair of transistors and said second pair of transistors;

self-biasing said first pair of transistors via said inductive loading; and

generating DC current via said second pair of transistors,

wherein when said first pair of transistors comprises PMOS transistors, then said second pair of transistors are NMOS transistors.

35. An apparatus for increasing output gain of an electronic circuit, the apparatus comprising:

a first pair of transistors and a second pair of transistors that each receives an input differential signal;

an inductive load that inductively loads said first pair of transistors and said second pair of transistors;

said inductive load self-biases said first pair of transistors; and

said second pair of transistors generates DC current,

wherein said second pair of transistors are PMOS transistors, when said first pair of transistors comprises NMOS transistors.

36. An apparatus for increasing output gain of an electronic circuit, the apparatus comprising:

a first pair of transistors and a second pair of transistors that each receives an input differential signal;

an inductive load that inductively loads said first pair of transistors and said second pair of transistors;

said inductive load self-biases said first pair of transistors; and

said second pair of transistors generates DC current,

wherein said second pair of transistors are NMOS transistors, when said first pair of transistors comprises PMOS transistors.

37. An apparatus for increasing gain for an electric circuit, the apparatus comprising:

a first transistor, wherein a gate of said first transistor is coupled to a first differential input;

a second transistor, wherein a gate of said second transistor is coupled to a second differential input;

a third transistor, wherein a gate of said third transistor is coupled to said first differential input; and

a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein;

said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;

said DC voltage source is coupled to said third transistor and said fourth transistor;

said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor; and

wherein said third transistor and said fourth transistor comprise PMOS transistors, when said first transistor and said second transistor comprise NMOS transistors.

38. An apparatus for increasing gain for an electric circuit, the apparatus comprising:

a first transistor, wherein a gate of said first transistor is coupled to a first differential input;

a second transistor, wherein a gate of said second transistor is coupled to a second differential input;

a third transistor, wherein a gate of said third transistor is coupled to said first differential input; and

a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein;

said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;

said DC voltage source is coupled to said third transistor and said fourth transistor;

said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor; and

wherein said third transistor and said fourth transistor comprise NMOS transistors, when said first transistor and said second transistor comprise PMOS transistors.

39. An apparatus for increasing gain for an electric circuit, the apparatus comprising:

a first transistor, wherein a gate of said first transistor is coupled to a first differential input;

a second transistor, wherein a gate of said second transistor is coupled to a second differential input;

a third transistor, wherein a gate of said third transistor is coupled to said first differential input;

a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein;

said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;

said DC voltage source is coupled to said third transistor and said fourth transistor;

said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor; and

a load inductor coupled to said DC voltage source.

40. An apparatus for increasing gain for an electric circuit, the apparatus comprising:

a first transistor, wherein a gate of said first transistor is coupled to a first differential input;

a second transistor, wherein a gate of said second transistor is coupled to a second differential input;

a third transistor, wherein a gate of said third transistor is coupled to said first differential input;

a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein;

said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;

said DC voltage source is coupled to said third transistor and said fourth transistor;

said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor; and

wherein a first terminal of a first resistor is coupled to said gate of said first transistor.

41. The apparatus according to claim 40, wherein a second terminal of said first resistor is coupled to said common mode output of said DC voltage source.

42. An apparatus for increasing gain for an electric circuit, the apparatus comprising:

a first transistor, wherein a gate of said first transistor is coupled to a first differential input;

a second transistor, wherein a gate of said second transistor is coupled to a second differential input;

a third transistor, wherein a gate of said third transistor is coupled to said first differential input;

a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein;

said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;

said DC voltage source is coupled to said third transistor and said fourth transistor;

said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor; and

wherein a first terminal of a second resistor is coupled to said gate of said second transistor.

43. The apparatus according to claim 42, wherein a second terminal of said second resistor is coupled to said common mode output of said DC voltage source.

44. An apparatus for increasing gain for an electric circuit, the apparatus comprising:

a first transistor, wherein a gate of said first transistor is coupled to a first differential input;

a second transistor, wherein a gate of said second transistor is coupled to a second differential input;

a third transistor, wherein a gate of said third transistor is coupled to said first differential input;

a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein;

said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;

said DC voltage source is coupled to said third transistor and said fourth transistor;

said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor; and

wherein a first terminal of a load inductor is coupled to a drain of said first transistor and a drain of said third transistor.

45. An apparatus for increasing gain for an electric circuit, the apparatus comprising:

a first transistor, wherein a gate of said first transistor is coupled to a first differential input;

a second transistor, wherein a gate of said second transistor is coupled to a second differential input;

a third transistor, wherein a gate of said third transistor is coupled to said first differential input; and

a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein;

said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;

said DC voltage source is coupled to said third transistor and said fourth transistor;

said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor; and

wherein a second terminal of a load inductor is coupled to a drain of said second transistor and a drain of said fourth transistor.