Flash ADC with variable LSB

• US 7,061,421 B1
• Filed: 03/31/2005
• Issued: 06/13/2006
• Est. Priority Date: 03/31/2005
• Status: Expired due to Fees

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Leung, Ka Y., Holberg, Douglas R., Xiao, Jinwen
• Primary Examiner(s): Nguyen, Linh V.
• Application Number:
  US11/096,163
• Time in Patent Office: 439 Days
• Field of Search: 341/154, 341/155, 341/156, 341/158, 341/159
• US Class Current: 341/155
• CPC Class Codes: H02M 3/33592 having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H03M 1/363 the voltage divider taps being held in a floating state, e.g. by feeding the divider by current sources
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A differential analog-to-digital data converter (ADC) is disclosed for receiving a positive input signal and a negative input signal. A distributed resistive device is provided having taps associated therewith. A plurality of comparators each having a signal input and a reference input are provided, the signal input connected to one of the positive and negative input signals and the reference input connected to a tap on said distributed resistive device. A driver drives current through the distributed resistive device with one of the taps of the distributed resistive device disposed at substantially the other of the positive and negative input signals. A current varying device varys the current through the distributed resistive device to vary the voltage between taps.

Claims

1. A differential analog-to-digital data converter (ADC) for receiving a positive input signal and a negative input signal, comprising:

a plurality of comparators each associated with a resolution bit of the data converter, one of the inputs of each of said comparators interfaced to a first analog input voltage and the other input of each of the comparators interfaced with a respective reference voltage;

a resolution bit reference device for generating a plurality of successively increasing voltages at respective reference nodes from a first voltage to a second voltage, each of said reference nodes connected to a respective one of the other inputs of said comparators to provide the respective reference voltage, and the voltage difference between said reference nodes defining the resolution of the data converter;

wherein for a substantially a zero difference between the positive and negative input signals, the voltage level of said first analog input voltage is disposed at a voltage above the voltage level on one of said reference nodes and below the voltage level on the next higher one of said reference nodes to constitute the zero code for the data converter; and

a resolution varying device to vary the voltages between said respective nodes in a manner such that the zero code does not substantially vary.

2. The ADC of claim 1, wherein the voltage difference between each of said reference nodes is substantially the same voltage.

3. The ADC of claim 1, wherein said first analog input voltage comprises one of the positive and negative input signals.

4. The ADC of claim 3, wherein the voltages on said reference nodes are referenced to the other of the positive and negative input signals.

5. The ADC of claim 1, wherein said resolution bit difference device comprises:

a plurality of series connected resistive devices wherein each of the junctions between said resistive devices comprises one of said respective reference nodes; and

a driver for driving current through said resistive devices.

6. The ADC of claim 5, wherein said driver comprises a current source having defined current driven through said resistive devices.

7. The ADC of claim 6, wherein the bit resolution of the ADC is greater than the number of said reference nodes.

8. The ADC of claim 7, wherein said first analog input voltage comprises one of the positive and negative input signals and the other of said positive and negative signals is coupled to the one of the reference nodes.

9. The ADC of claim 8, wherein said resolution varying device comprises a current varying device for varying the current through said current source.

10. A differential analog-to-digital data converter (ADC) for receiving a positive input signal and a negative input signal, comprising:

a distributed resistive device having taps associated therewith;

a plurality of comparators each having a signal input connected to one of the positive and negative input signals and a reference input connected to a tap on said distributed resistive device;

a driver for driving current through said distributed resistive device with one of the taps of said distributed resistive device disposed at substantially the other of said positive and negative input signals; and

a current varying device for varying the current through said distributed resistive device to vary the voltage between taps and maintain the zero code unvarying.

11. The ADC of claim 10, wherein the voltage difference between adjacent ones of said taps is substantially the same voltage.

12. The ADC of claim 10, wherein said driver comprises:

a buffer circuit having the input thereof connected to the other of said positive and negative input signals and the output thereof connected to the one of the taps of said distributed resistive device; and

a current source for driving a known current through said distributed resistance device.

13. The ADC of claim 12, wherein said distributed resistive device comprises a plurality of series connected resistors connected between a first node and a second node and said current source driving current between said first and second nodes, the junctions between said series connected resistors comprising said taps connected to the reference inputs of respective ones of said comparators.

14. The ADC of claim 13, wherein the ADC has a finite resolution defined by the voltage across said resistors that comprises the size of the least significant bit (LSB) of the ADC, and the full number of bits of the ADC greater than the number of said series connected resistors.

15. The ADC of claim 14, wherein said current varying device is operable to vary the current through said current source, and thus vary the size of the LSB.

16. The ADC of claim 12, wherein said current source is variable and said current varying device is operable to vary current provided by said current source.

17. The ACD of claim 16, wherein said current source is referred to a stable fixed current source and said current varying device is operable vary the current through said distributed resistive device in a ratiometric manner.