Semiconductor integrated circuit

• US 7,061,530 B2
• Filed: 06/20/2001
• Issued: 06/13/2006
• Est. Priority Date: 06/20/2000
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Koyama, Eiji
• Primary Examiner(s): Vu, Ngoc-Yen
• Assistant Examiner(s): Villecco, John M.
• Application Number:
  US09/883,990
• Publication Number:
  US 20020047632A1
• Time in Patent Office: 1,819 Days
• Field of Search: 348/241, 348/312, 348/208.16, 348/211.9, 348/222.1, 348/296, 348/304, 326/96, 327/3, 327/5, 327/7, 327/10, 327/37, 327/40, 327/58, 327/60, 327/62, 327/74, 315/291
• US Class Current: 348/241
• CPC Class Codes: H03M 1/08 of noise H03M1/0617 takes precedence
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/617 for reducing electromagnetic interference, e.g. clocking noise
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/7795 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

Even when variation in transistor characteristic, resistance or the like occurs during manufacturing, a noise component is always minimized. Each of k clock phase difference generating circuits 16–18 shifts a phase of a basic clock signal ADCK1 by a specified different value to obtain a clock signal ADCK2 and supplies the clock signal ADCK2 to an A/D converter. A k counter 19 successively selects the clock phase difference generating circuits 16–18 and stores a noise component in an output of the A/D converter measured by a noise measuring circuit 27 in a corresponding register. A comparator 25 compares k noise components and obtains the number j of the clock phase difference generating circuit giving a minimum value. A selection circuit 26 fixedly selects only the j-th clock phase difference generating circuit. Thus, even when variation in the transistor characteristics or resistance occurs in each device in a manufacturing stage, the clock signal ADCK2 obtained by shifting the phase of the basic clock signal ADCK1 can be supplied to the A/D converter so that a noise component is minimized for each device.

Claims

1. A semiconductor integrated circuit wherein an analog circuit operating in response to a first clock signal and a digital circuit operating in response to a second clock signal having the same period as that of the first clock signal are formed on the same semiconductor substrate;

comprising on the semiconductor substrate;

a plurality of phase shift circuits each relatively shifting a phase of one of the first clock signal and the second clock signal from a phase of the other of the first clock signal and the second clock signal by a different value;

a noise measuring circuit for measuring a noise component generated by the analog circuit,

wherein the noise component is measured during a manufacturing stage;

selection control means for successively replacing and selecting the plurality of phase shift circuits during the manufacturing stage;

phase shift setting means for obtaining a minimum value out of the noise components measured when each of the phase shift circuits is selected and setting a phase shift value by fixedly selecting only a phase shift circuit selected when the noise component assumes the minimum value;

operation start control means for starting an operation of the selection control means when a first specified time elapses after having powered on; and

time measuring means for measuring a second specified time after termination of successive selection of the phase shift circuits by the selection control means, and operating the selection control means when the second specified time elapses, wherein

successive selection of the phase shift circuits is repeated at intervals of the second specified time.

2. A semiconductor integrated circuit wherein an analog circuit operating in response to a first clock signal and a digital circuit operating in response to a second clock signal having the same period as that of the first clock signal are formed on the same semiconductor substrate;

comprising on the semiconductor substrate;

a plurality of phase shift circuits each relatively shifting a phase of one of the first clock signal and the second clock signal from a phase of the other of the first clock signal and the second clock signal by a different value;

a noise measuring circuit for measuring a noise component generated by the analog circuit,

wherein the noise component is measured during a manufacturing stage;

selection control means for successively replacing and selecting the plurality of phase shift circuits during the manufacturing stage; and

phase shift setting means for obtaining a minimum value out of the noise components measured when each of the phase shift circuits is selected and setting a phase shift value by fixedly selecting only a phase shift circuit selected when the noise component assumes the minimum value

wherein

the analog circuit is a solid-state image sensing element array; and

the noise component measured by the noise measuring circuit is a noise component superimposed on a video signal of a shielded region outputted from the solid-state image sensing element array during one valid horizontal period; and

successive selection of the phase shift circuits by the selection control means is performed in synchronization with a vertical period.