Array substrate having double-layered metal patterns and method of fabricating the same

• US 7,061,565 B2
• Filed: 10/16/2003
• Issued: 06/13/2006
• Est. Priority Date: 11/08/2002
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Lee, Kyoung-Mook, Kwon, Oh-Nam, Choi, Nack-Bong
• Primary Examiner(s): Schechter, Andrew
• Assistant Examiner(s): Nguyen, Hoan C.
• Application Number:
  US10/685,419
• Publication Number:
  US 20050018097A1
• Time in Patent Office: 971 Days
• Field of Search: 349/139, 349/43, 257/57, 257/59, 257/66, 257/72, 257/770, 257/763, 257/762, 348/158, 348/584, 348/597, 348/648, 348/642, 348/683, 348/687, 348/685
• US Class Current: 349/139
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

An array substrate having double-layered metal patterns for use in a liquid crystal display device and a manufacturing method thereof are disclosed in the present invention. The array substrate includes a gate electrode and a gate line each having a molybdenum alloy (Mo-alloy) layer and a copper (Cu) layer configured sequentially on a substrate; a gate insulation layer on the substrate to cover the gate electrode and the gate line; an active layer arranged on the gate insulation layer in a portion over the gate electrode; an ohmic contact layer on the active layer; a data line on the gate insulation layer, the data line crossing the gate line and defining a pixel region; source and drain electrodes on the ohmic contact layer, the source electrode extending from the data line, and the drain electrode spaced apart from the source electrode; a passivation layer on the gate insulation layer covering the data line and the source and drain electrode, the passivation layer having a drain contact hole exposing a portion of the drain electrode; and a pixel electrode configured on the passivation layer in the pixel region, the pixel electrode electrically contacting the drain electrode through the drain contact hole.

Claims

1. An array substrate for use in a liquid crystal display device, comprising:

a gate electrode and a gate line, each having a molybdenum alloy (Mo-alloy) layer including one of tungsten (W), neodymium (Nd), niobium (Nb) and the combination thereof and a copper (Cu) layer on a substrate,

wherein the Mo-alloy layer is formed on the substrate and the Cu layer is formed on the Mo-alloy layer;

a gate insulation layer on the substrate to cover the gate electrode and the gate line;

an active layer arranged on the gate insulation layer in a portion over the gate electrode;

an ohmic contact layer on the active layer;

a data line on the gate insulation layer, the data line crossing the gate line and defining a pixel region;

source and drain electrodes on the ohmic contact layer, the source electrode extending from the data line, and the drain electrode spaced apart from the source electrode;

a passivation layer on the gate insulation layer covering the data line and the source and drain electrodes, the passivation layer having a drain contact hole exposing a portion of the drain electrode; and

a pixel electrode configured on the passivation layer in the pixel region, the pixel electrode electrically contacting the drain electrode through the drain contact hole.

2. The substrate according to claim 1, further comprising a storage metal layer configured over a portion of the gate line.

3. The substrate according to claim 2, wherein the storage metal layer is formed with the data line on the gate insulation layer.

4. The substrate according to claim 2, wherein the pixel electrode electrically contacts the storage metal layer via a storage contact hole.

5. The substrate according to claim 2, wherein the data line, the source electrode, the drain electrode and the storage metal layer are all formed of a double-layered metal pattern consisting of a lower part of molybdenum alloy (Mo-alloy) and an upper part of copper (Cu).

6. The substrate according to claim 5, wherein the molybdenum alloy (Mo-alloy) includes one of tungsten (W), neodymium (Nd), niobium (Nb) and the combination thereof.

7. The substrate according to claim 2, wherein the data line, the source electrode, the drain electrode and the storage metal layer are all formed of a single layer of copper (Cu).

8. The substrate according to claim 1, wherein the molybdenum alloy layer of the gate electrode and gate line has a thickness in a range from about 10 to about 500 angstroms.

9. The substrate according to claim 1, wherein the copper layer has a thickness in a range from about 500 to about 5000 angstroms.