Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states

• US 7,061,798 B2
• Filed: 10/15/2004
• Issued: 06/13/2006
• Est. Priority Date: 06/27/2001
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), SanDisk Corporation (Western Digital Corporation)
• Inventors: Chen, Jian, Tanaka, Tomoharu, Quader, Khandker N., Fong, Yupin
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US10/966,451
• Publication Number:
  US 20050047223A1
• Time in Patent Office: 606 Days
• Field of Search: 365/185.02, 365/185.03, 365/185.17, 365/185.18, 365/185.22
• US Class Current: 365/185.02
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

Claims

1. A method of operating a non-volatile memory having an array of semiconductor memory cells organized into blocks that are erased together prior to re-programming memory cells thereof, wherein charge levels stored in some charge storage elements of the memory cells affect readings from other charge storage elements on account of at least electric field coupling between neighboring storage elements, comprising:

storing in a first group of storage elements a first set of charge levels corresponding to a first set of data,

thereafter storing in a second group of storage elements different from the first group a second set of charge levels corresponding to a second set of data, wherein at least some of the stored second set of charge levels affect values read from memory cells including at least some of the first group of storage elements because of at least field coupling between the storage elements, and

altering the first set of stored charge levels of the first group of storage elements in order to counteract an effect of the second set of stored charge levels on the values read from memory cells including at least some of the first group of storage elements because of field coupling between the storage elements, thereby to facilitate accurate reading of the first set of data from the first group of storage elements.

2. The method of claim 1, wherein a characteristic of the first set of stored charge levels that is affected by the second set of stored charge levels includes broadening an apparent distribution of those of the stored first set of levels that correspond to particular states of the first set of data, and wherein altering the first set of stored charge levels includes compacting the distribution of those of the stored first set of levels that correspond to particular states of the first set of data.

3. The method of claim 2, wherein compacting the distribution occurs after storing the second set of charge levels.

4. The method of claim 3, additionally comprising, prior to compacting the distribution of the stored first set of charge levels, reading the first set of data from the first group of storage elements.

5. The method of claim 2, wherein compacting the distribution occurs before storing the second set of charge levels.

6. The method of claim 1, wherein the storage elements are electrically conductive floating gates, and wherein the charge levels stored thereon affect conduction through memory cell transistors of which the storage elements are a part.

7. The method of claim 6, wherein more than two stored charge levels are defined for individual ones of the floating gates in order to store more than one bit of data on the individual floating gates.

8. The method of claim 1, wherein the non-volatile memory system in which the operating method is carried out includes an array of flash electrically erasable and programmable read only memory (EEPROM) cells having storage elements in the form of at least one floating gate per cell.

9. The method of claim 8, wherein the non-volatile memory system in which the operating method is carried out includes memory cells having two floating gates per cell.

10. The method of claim 8, wherein the non-volatile memory system in which the operating method is carried out includes memory cells organized in a NAND architecture.

11. The method of claim 1, wherein altering the first set of stored charge levels includes reading the first set of data from the first group of storage elements and thereafter restoring in the first group of storage elements the first set of charge levels corresponding to the read first set of data, whereby the restoring is accomplished without having to retain a copy of the first set of data initially stored in the first group of storage elements.

12. The method of claim 1, wherein the storage elements are operated to individually have a storage window divided into a plurality of defined ranges of charge levels representative of more than one bit of data and which are separated from one another, and the data are stored in the individual storage elements by incrementally changing the charge levels thereof until one of the charge level ranges is reached that corresponds to the data being stored therein, and further

wherein storing the first set of charge levels in the first group of storage elements includes incrementally changing the charge levels of individual storage elements until one of a first set of reference storage levels corresponding to the data being stored is reached or exceeded, thereby to store the data with distributions of charge levels among the plurality of storage elements within defined ranges having widths resulting from incrementally changing the charge levels, and

wherein altering the first set of charge levels stored in the first group of storage elements includes restoring charge levels in one portion of individual ones of said distributions by incrementally changing the charge levels of those individual storage elements until the stored charge levels are moved to another non-overlapping portion of their respective distributions, the amount of incremental change during storing being greater than the incremental change of storage levels during restoring.

13. The method of claim 12, wherein the memory system storage elements include conductive floating gates.

14. The method of claim 12, wherein the storage elements are connected in a NAND arrangement.