Data path having grounded precharge operation and test compression capability

• US 7,061,817 B2
• Filed: 06/30/2004
• Issued: 06/13/2006
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Micron Technology, Inc.
• Inventors: Jung, Chulmin, Raad, George
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, DANG T
• Application Number:
  US10/883,619
• Publication Number:
  US 20060002206A1
• Time in Patent Office: 713 Days
• Field of Search: 365/201, 365/203, 365/190, 365/63, 365/230.06, 365/191, 365/189.01
• US Class Current: 365/201
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 29/40 using compression techniques

Abstract

A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.

Claims

1. A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier, the data path comprising:

a pair of global input/output (GIO) signal lines coupled to an input of the IO line sense amplifier;

a pair of local input/output (LIO) signal lines having coupled to a column of memory including the memory cell during a memory read or write operation;

an IO line coupling circuit coupled to the GIO and LIO signal lines, the coupling circuit operable for the memory read operation to couple and decouple each of the GIO signal lines to and from a voltage supply in accordance with voltage levels of the LIO signal lines and further operable for the memory write operation to couple and decouple each of the GIO signal lines to and from a respective one of the LIO signal lines; and

a first precharge circuit coupled to the GIO signal lines and operable to couple the GIO signal lines to ground to precharge the signal lines prior to a memory read or write operation.

2. The data path of claim 1, further comprising a second precharge circuit coupled to the LIO signal lines and operable to couple the LIO signal lines to the voltage supply to precharge the signal lines prior to a memory read or write operation.

3. The data path of claim 1 wherein the IO line coupling circuit comprises:

a pair of p-channel MOS transistors, each having a source coupled to the voltage supply and a drain, each p-channel MOS transistor further having a gate coupled to receive a read activation signal;

a first pair of n-channel MOS transistors, each having a drain coupled to the drain of a respective one of the p-channel MOS transistors and having a source coupled to a respective one of the GIO signal lines, each n-channel MOS transistor further having a gate coupled to a respective one of the LIO signal lines; and

a second pair of n-channel MOS transistors, each having a drain coupled to a respective one of the GIO signal lines and a source coupled to a respective one of the LIO signal lines, and further having a gate coupled to receive a write activation signal.

4. The data path of claim 1 wherein the GIO signal line has an inherent capacitance greater than the inherent capacitance of the LIO signal lines.

5. The data path of claim 1, further comprising a test compression circuit coupled to the GIO signal lines operable in a test mode to compare voltage levels of each of the respective GIO signal lines to a reference voltage, and in response, generate an output test signal indicative of whether the voltage levels of the GIO signal lines relative to the reference voltage are complementary or the same.

6. The data path of claim 5 wherein the test compression circuit comprises:

first and second voltage comparison circuits, each voltage comparison circuit coupled to a respective one of the GIO signal lines and having differential amplifier having a first input coupled to the respective GIO signal line and a second input coupled to a reference voltage supply, each voltage comparison circuit having an amplifier stage coupled to the differential amplifier stage to amplify the voltage difference between the voltage level of the GIO signal line to which the differential amplifier stage is coupled and the reference voltage, and further having an output stage to provide output signals indicative of the amplified voltage difference; and

a logic circuit coupled to the output stages of the first and second voltage comparison circuits operable to compare the output signals of the first and second voltage comparison circuits and generate in response test compression signals indicative of whether the voltage levels of the GIO signal lines relative to the reference voltage complementary or the same.

7. A memory device, comprising:

an address bus;

a control bus;

an address decoder coupled to the address bus;

a control circuit coupled to the control bus;

a memory-cell array coupled to the address decoder and control circuit

a read/write circuit coupled to the memory-cell array;

an output data buffer; and

a data path coupled to a read/write circuit and the output data buffer for coupling data between a memory cell and an input/output (IO) line sense amplifier, the data path comprising;

a pair of global input/output (GIO) signal lines coupled to an input of the IO line sense amplifier;

a pair of local input/output (LIO) signal lines having coupled to a column of memory including the memory cell during a memory read or write operation;

an IO line coupling circuit coupled to the GIO and LIO signal lines, the coupling circuit operable for the memory read operation to couple and decouple each of the GIO signal lines to and from a voltage supply in accordance with voltage levels of the LIO signal lines and further operable for the memory write operation to couple and decouple each of the GIO signal lines to and from a respective one of the LIO signal lines; and

a first precharge circuit coupled to the GIO signal lines and operable to couple the GIO signal lines to ground to precharge the signal lines prior to a memory read or write operation.

8. The memory device of claim 7 wherein the data path further comprises a second precharge circuit coupled to the LIO signal lines and operable to couple the LIO signal lines to the voltage supply to precharge the signal lines prior to a memory read or write operation.

9. The memory device of claim 7 wherein the IO line coupling circuit of the data path comprises:

a pair of p-channel MOS transistors, each having a source coupled to the voltage supply and a drain, each p-channel MOS transistor further having a gate coupled to receive a read activation signal;

a first pair of n-channel MOS transistors, each having a drain coupled to the drain of a respective one of the p-channel MOS transistors and having a source coupled to a respective one of the GIO signal lines, each n-channel MOS transistor further having a gate coupled to a respective one of the LIO signal lines; and

a second pair of n-channel MOS transistors, each having a drain coupled to a respective one of the GIO signal lines and a source coupled to a respective one of the LIO signal lines, and further having a gate coupled to receive a write activation signal.

10. The memory device of claim 7 wherein the GIO signal line of the data path has an inherent capacitance greater than the inherent capacitance of the LIO signal lines.

11. The memory device of claim 7 wherein the data line further comprises a test compression circuit coupled to the GIO signal lines operable in a test mode to compare voltage levels of each of the respective GIO signal lines to a reference voltage, and in response, generate an output test signal indicative of whether the voltage levels of the GIO signal lines relative to the reference voltage are complementary or the same.

12. The memory device of claim 11 wherein the test compression circuit comprises:

first and second voltage comparison circuits, each voltage comparison circuit coupled to a respective one of the GIO signal lines and having differential amplifier having a first input coupled to the respective GIO signal line and a second input coupled to a reference voltage supply, each voltage comparison circuit having an amplifier stage coupled to the differential amplifier stage to amplify the voltage difference between the voltage level of the GIO signal line to which the differential amplifier stage is coupled and the reference voltage, and further having an output stage to provide output signals indicative of the amplified voltage difference; and

a logic circuit coupled to the output stages of the first and second voltage comparison circuits operable to compare the output signals of the first and second voltage comparison circuits and generate in response test compression signals indicative of whether the voltage levels of the GIO signal lines relative to the reference voltage complementary or the same.

13. A processor-based system, comprising:

a data input device;

a data output device;

a processor coupled to the data input and output devices; and

a memory device coupled to the processor, the memory device comprising;

an address bus;

a control bus;

an address decoder coupled to the address bus;

a control circuit coupled to the control bus;

a memory-cell array coupled to the address decoder and control circuit

a read/write circuit coupled to the memory-cell array;

an output data buffer; and

a data path coupled to a read/write circuit and the output data buffer for coupling data between a memory cell and an input/output (IO) line sense amplifier, the data path comprising;

a pair of global input/output (GIO) signal lines coupled to an input of the IO line sense amplifier;

a pair of local input/output (LIO) signal lines having coupled to a column of memory including the memory cell during a memory read or write operation;

an IO line coupling circuit coupled to the GIO and LIO signal lines, the coupling circuit operable for the memory read operation to couple and decouple each of the GIO signal lines to and from a voltage supply in accordance with voltage levels of the LIO signal lines and further operable for the memory write operation to couple and decouple each of the GIO signal lines to and from a respective one of the LIO signal lines; and

a first precharge circuit coupled to the GIO signal lines and operable to couple the GIO signal lines to ground to precharge the signal lines prior to a memory read or write operation.

14. The processor-based system of claim 13 wherein the data path further comprises a second precharge circuit coupled to the LIO signal lines and operable to couple the LIO signal lines to the voltage supply to precharge the signal lines prior to a memory read or write operation.

15. The processor-based system of claim 13 wherein the IO line coupling circuit of the data path comprises:

a pair of p-channel MOS transistors, each having a source coupled to the voltage supply and a drain, each p-channel MOS transistor further having a gate coupled to receive a read activation signal;

a first pair of n-channel MOS transistors, each having a drain coupled to the drain of a respective one of the p-channel MOS transistors and having a source coupled to a respective one of the GIO signal lines, each n-channel MOS transistor further having a gate coupled to a respective one of the LIO signal lines; and

a second pair of n-channel MOS transistors, each having a drain coupled to a respective one of the GIO signal lines and a source coupled to a respective one of the LIO signal lines, and further having a gate coupled to receive a write activation signal.

16. The processor-based system of claim 13 wherein the GIO signal line of the data path has an inherent capacitance greater than the inherent capacitance of the LIO signal lines.

17. The processor-based system of claim 13 wherein the data line further comprises a test compression circuit coupled to the GIO signal lines operable in a test mode to compare voltage levels of each of the respective GIO signal lines to a reference voltage, and in response, generate an output test signal indicative of whether the voltage levels of the GIO signal lines relative to the reference voltage are complementary or the same.

18. The processor-based system of claim 17 wherein the test compression circuit comprises:

first and second voltage comparison circuits, each voltage comparison circuit coupled to a respective one of the GIO signal lines and having differential amplifier having a first input coupled to the respective GIO signal line and a second input coupled to a reference voltage supply, each voltage comparison circuit having an amplifier stage coupled to the differential amplifier stage to amplify the voltage difference between the voltage level of the GIO signal line to which the differential amplifier stage is coupled and the reference voltage, and further having an output stage to provide output signals indicative of the amplified voltage difference; and

a logic circuit coupled to the output stages of the first and second voltage comparison circuits operable to compare the output signals of the first and second voltage comparison circuits and generate in response test compression signals indicative of whether the voltage levels of the GIO signal lines relative to the reference voltage complementary or the same.

19. A method for coupling data between a memory cell in a memory array to and from an input/output sense amplifier, the method comprising:

precharging a pair of global data lines to ground;

in the event of a read operation, coupling the global data lines to a voltage supply, coupling the data from the memory cell and complementary data to a pair of local data lines, and decoupling one of the global data lines from the voltage supply based on the data and its complement coupled to the local data lines; and

in the event of a write operation, coupling the memory cell to the pair of local data lines, coupling each of the global data signal lines to a respective one of the local data lines, and coupling complementary data representing the data to be written to the memory cell to the global data signal lines.

20. The method of claim 19, further comprising precharging the local data lines to an internal voltage level.

21. The method of claim 19, further comprising:

generating complementary voltage signals representative of the data of the memory cell;

coupling the complementary voltage signals to the pair of local data lines; and

switching off one of a pair of switches coupling the global data line to the voltage supply.