Wireless computer network including a mobile appliance containing a single chip transceiver

• US 7,061,855 B2
• Filed: 06/27/2005
• Issued: 06/13/2006
• Est. Priority Date: 03/19/2001
• Status: Expired due to Term

• Current Assignee: Cisco Systems Wireless Networking (Australia) Pty Limited (Cisco Systems, Inc.)
• Original Assignee: Cisco Systems Wireless Networking (Australia) Pty Limited (Cisco Systems, Inc.)
• Inventors: Adams, Andrew, Keaney, Richard, Ryan, Philip, Weste, Neil, Skellern, David J., O'Sullivan, John
• Primary Examiner(s): Nguyen, Chau
• Assistant Examiner(s): Cho, Hong Sol
• Application Number:
  US11/168,011
• Publication Number:
  US 20050237924A1
• Time in Patent Office: 351 Days
• Field of Search: 370/208, 370/480, 370/338, 370/401, 370/328, 370/210, 455/84, 375/238
• US Class Current: 370/208
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/405 with multiple discrete channels

Abstract

A wireless computer data network includes several untethered mobile units that make ad-hoc data connections with an Internet-connected base station using the IEEE-802.11a standard. Each unit includes a radio transceiver fully integrated on a single semiconductor chip. The receiver portion is a double-conversion superheterodyne type, and shares the same intermediate and local oscillator frequencies with a two-stage up-conversion transmitter. Two on-chip synthesizers that each include a voltage-controlled oscillator and phase-locked loop can be operated independently for each conversion stage, or operated in offset mode. External reference frequencies can be injected for voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling. Each mobile and base unit can be outfitted with transmit/receive antenna transfer switches, RF-power amplifiers, and low-noise receiver amplifiers to increase operating range.

Claims

1. A first wireless appliance of a wireless computer data network, the network including at least one other wireless appliance and a base station connected to a network that includes a wired section, the first wireless appliance comprising:

an interface circuit for establishing a radio communication link between the first wireless appliance and the base station, the interface circuit configured for operating with carrier frequencies in the 5 GHz band and for transferring data with orthogonal frequency division multiplexing (OFDM); and

a single integrated circuit that implements a complete radio transceiver for wireless connection with the interface circuit, wherein said single integrated circuit includes at least two frequency synthesizers connected in a double-conversion superheterodyne configuration.

2. A first wireless appliance as recited in claim 1, wherein the network that includes a wired section is the Internet.

3. A first mobile, wireless appliance for operation in a wireless computer data network, the first wireless appliance comprising:

a single integrated circuit that implements a complete radio transceiver for wireless connection with an interface circuit,

wherein the single integrated circuit comprises;

at least two independent frequency synthesizers connected in a double-conversion superheterodyne configuration,

wherein the wireless computer data network includes;

at least one base station connected to the Internet; and

a plurality of wireless appliances including the first wireless appliance,

wherein the interface circuit is arranged for establishing an ad-hoc radio communication link amongst the plurality of wireless appliances and base station, and

wherein the interface circuit operates with carrier frequencies in at least the 5 GHz band and data is transferred with orthogonal frequency division multiplexing (OFDM).

4. A single-chip radio transceiver for operation in at least the 5 GHz radio spectrum, comprising:

a double-conversion superheterodyne radio receiver;

a two-stage up-conversion radio transmitter;

a first frequency synthesizer connected to supply a higher local oscillator reference frequency to both the receiver and transmitter,

a second frequency synthesizer, connected to supply a lower local oscillator reference frequency to both the receiver and transmitter; and

a microcomputer connected to monitor and control each of the receiver, transmitter, and the first and second frequency synthesizers.

5. A single-chip radio transceiver as recited in claim 4, wherein the microcomputer compensates for temperature variations according to device characteristic models.

6. A single-chip radio transceiver as recited in claim 4, further comprising:

an input provided for injecting an external reference frequency during voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling,

wherein, the microcomputer thereafter compensates during device operation for production and temperature variations.

7. A first untethered mobile unit of a wireless computer data network that includes a plurality of untethered mobile units, the first untethered mobile unit comprising:

a radio transceiver integrated on a single semiconductor chip, the radio transceiver including;

a double-conversion superheterodyne type receiver portion;

a two-stage up-conversion transmitter; and

a pair of on-chip synthesizers that each have a voltage-controlled oscillator and phase-locked loop that can be operated independently for each conversion stage, or operated in offset mode,

wherein the receiver and transmitter share the same intermediate and local oscillator frequencies,

wherein an input is provided on the transceiver for injecting external reference frequencies during voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling,

wherein the wireless computer data network provides for ad-hoc data connections with a base station using an IEEE-802.11 OFDM standard, and

wherein the base station is connected to a network that includes a wired section.

8. A first wireless appliance as recited in claim 7, wherein the network that includes a wired section is the Internet.

9. A wireless communication station for operation in an IEEE-802.11-compliant wireless network, the wireless communication station comprising:

a physical layer interface (PHY) that includes an antenna for 5 GHz carrier service, a transmit/receive (T/R) switch for half-duplex operation, a radio transceiver integrated on a single semiconductor chip, and a data modem integrated on a single semiconductor chip, the radio transceiver including;

a radio frequency low-noise amplifier (LNA), A RF receiver, a RF transmitter, and a RF power amplifier (PA);

an IEEE-802.11-compliant media access controller (MAC) for ISO-defined layer-2 processing; and

a static random access memory (SRAM) for data buffering and program storage.

10. A wireless communication station as recited in claim 9, wherein the RF receiver is a double-conversion superheterodyne type receiver, and wherein the RF transmitter is a two-stage up-conversion transmitter.

11. A wireless communication station as recited in claim 9, wherein the radio transceiver includes a ramp and bias generator for selectively and gradually applying operating power to the power amplifier.

12. A wireless communication station as recited in claim 9, wherein the radio transceiver includes a plurality of ramp and bias generators for selectively and gradually applying operating power to various parts of the receiver, transmitter, and the power amplifier.

13. A wireless communication station as recited in claim 9, further comprising:

a PCMCIA wireless LAN card on which the PHY, MAC, and SRAM are fully disposed,

wherein the LAN card is constructed on a single printed circuit board (PCB) and the RF transceiver and modem are implemented with CMOS technology.

14. A first wireless appliance means for mobile roaming within reach of an ad-hoc wireless communication link in a wireless computer data network, the first wireless appliance means comprising:

an interface means for establishing said ad-hoc radio communication link, and for operating with carrier frequencies in the 5 GHz band, and for transferring orthogonal frequency division multiplexing (OFDM) data; and

a single integrated circuit means for implementing a single radio transceiver portion of the interface means, the single integrated circuit means including at least two independent frequency synthesizer means for connection in a double-conversion superheterodyne configuration,

wherein the wireless computer data network includes at least one base station means for connecting the first wireless appliance means to the internet over said ad-hoc wireless communication link.

15. A single-chip radio transceiver for operation in the 5 GHz radio spectrum, comprising:

means for double-conversion superheterodyne radio reception;

means for two-stage up-conversion radio transmission;

means for synthesizing and connecting a first frequency synthesizer to supply a higher local oscillator reference frequency to both the reception and transmission means;

means for connecting a second frequency synthesizer independent of the first frequency synthesizer, and for connecting to supply a lower local oscillator reference frequency to both the receiver and transmitter of the transceiver; and

microcomputer means for monitoring and controlling ramp and bias generator means, the reception and transmission means, and said first and second frequency synthesizers.

16. The single-chip radio transceiver of claim 15, wherein the microcomputer means includes means for compensating any manufacturing production variations by adjusting an output provided to the ramp and bias generator means.

17. The single-chip radio transceiver of claim 15, wherein the microcomputer means compensates for temperature variations according to device characteristic models.

18. The single-chip radio transceiver of claim 15, further comprising:

an input means for injecting an external reference frequency during voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling,

wherein, the microcomputer means thereafter compensates during device operation for production and temperature variations.