Method and device for providing hidden storage in non-volatile memory

• US 7,062,623 B2
• Filed: 09/26/2003
• Issued: 06/13/2006
• Est. Priority Date: 06/30/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Brizek, John P., Hasbun, Robert N., Vogt, James R.
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US10/672,593
• Publication Number:
  US 20040078511A1
• Time in Patent Office: 991 Days
• Field of Search: 365/189.04, 365/189.12, 365/194, 711/100, 711/102, 711/103, 711/154, 711/163, 711/164, 380/1
• US Class Current: 711/164
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

A method and device for providing hidden storage in non-volatile memory. A memory device is disclosed comprising a main flash array. A hidden storage area is connected to the main flash array. The hidden storage area can not be accessed without a valid password according to the present memory device.

Claims

1. A memory device comprising:

a main memory array;

an internal processor to execute programming code;

a hidden storage area coupled with the main memory array, wherein the programming code prevents access to the hidden storage area if a password is invalid; and

a bad password counter coupled with the internal processor to maintain a record of one or more invalid passwords, wherein if the bad password counter reaches a predetermined maximum value the internal processor stops processing password verification commands.

2. The memory device of claim 1, wherein the main memory array comprises a non-volatile writable memory array.

3. The memory device of claim 2, wherein the non-volatile writable memory array comprises one or more of the following:

a flash memory array, a battery backed memory array, and a polymer memory array.

4. The memory device of claim 1, wherein the hidden storage area comprises one or more hidden memory banks.

5. The memory device of claim 4, wherein the hidden memory banks are divided into one or more user spaces and a password space containing one or more stored valid reference passwords.

6. The memory device of claim 5, wherein the valid password allows access to one of the user spaces.

7. The memory device of claim 4, wherein the hidden memory banks include a swap space to copy data between the hidden memory banks without exposing the data in the hidden memory banks.

8. The memory device of claim 4, wherein the hidden storage area further comprises a bank selector to select a hidden memory bank.

9. The memory device of claim 4, wherein the hidden storage area further comprises an output bus gate to prevent access to the hidden memory banks.

10. The memory device of claim 9, wherein the hidden storage area further comprises an address decoder to open the output bus gate when provided the valid password.

11. The memory device of claim 9, wherein the hidden storage further comprises an address decoder to open the output bus gate when a valid memory address within the hidden memory banks is provided.

12. A method, comprising:

storing one or more valid passwords in a hidden memory area;

receiving a password at an internal processor coupled with the hidden memory area;

executing programming code to verify the password against a valid reference password stored within the hidden memory area; and

maintaining a record of one or more invalid passwords at a bad password counter coupled with the internal processor, wherein if the bad password counter reaches a predetermined maximum value the internal processor stops processing password verification commands.

13. The method of claim 12, further comprising permitting access to read from the hidden memory area if the password is verified.

14. The method of claim 12, further comprising permitting access to write to the hidden memory area if the password is verified.

15. The method of claim 12, further comprising permitting access to write to the hidden memory are if a valid address in the hidden memory area is provided.

16. The method of claim 12, further comprising dividing the hidden memory area into one or more of user spaces, a password space, and a swap space.

17. The method of claim 12, further comprising writing a recovery password that allows the bad password counter to be reset.

18. The method of claim 12, further comprising writing a system administrator password that allows the hidden memory area contents to be reset.

19. The method of claim 12, further comprising writing a system administrator password that allows a recovery password to be reset.

20. The method of claim 12, further comprising writing a system administrator password that allows the bad password counter to be reset.

21. A machine-readable medium having stored thereon data representing sets of instructions which, when executed by a machine, cause the machine to:

store one or more valid passwords in a hidden memory area;

receive a password at an internal processor connected to the hidden memory area;

execute programming code to verify the password against a valid reference password stored within the hidden memory area; and

maintain a record of one or more invalid passwords at a bad password counter coupled with the internal processor, wherein if the bad password counter reaches a predetermined maximum value the internal processor stops processing password verification commands.

22. The machine-readable medium of claim 21, wherein the sets of instructions which, when executed by the machine, further cause the machine to read from the hidden memory area if the password is verified.

23. The machine-readable medium of claim 21, wherein the sets of instructions which, when executed by the machine, further cause the machine to write to the hidden memory are if the password is verified and a valid address in the hidden memory is provided.

24. The machine-readable medium of claim 21, wherein the sets of instructions which, when executed by the machine, further cause the machine to divide the hidden memory area into one or more of user spaces, a password space, and a swap space.

25. The machine-readable medium of claim 21, wherein the sets of instructions which, when executed by the machine, further cause the machine to write a system administrator password that allows hidden memory area content to be reset.

26. A system comprising:

a wireless communication transceiver; and

a memory device coupled with the wireless communication transceiver, the memory device including

a main memory array,

an internal processor to execute programming code,

a hidden storage area connected to the main memory array, wherein the programming code prevents access to the hidden storage area without a valid password, and

a bad password counter coupled with the internal processor to maintain a record of one or more invalid passwords.

27. The system of claim 26, wherein the main memory array comprises a non-volatile writable memory array.

28. The system of claim 27, wherein the non-volatile writable memory array comprises one or more of the following:

a flash memory array, a battery backed memory array, and a polymer memory array.

29. The system of claim 26, wherein the hidden storage area comprises one or more hidden memory banks.