16 QAM and 16 APSK TTCM (Turbo Trellis Coded Modulation) with minimum bandwidth efficiency of 3 bit/s/Hz using a rate 2/4 constituent encoder

• US 7,062,700 B2
• Filed: 08/07/2003
• Issued: 06/13/2006
• Est. Priority Date: 05/31/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Tran, Hau Thien, Cameron, Kelly Brian
• Primary Examiner(s): Lamarre, Guy J.
• Application Number:
  US10/636,008
• Publication Number:
  US 20040261003A1
• Time in Patent Office: 1,041 Days
• Field of Search: 714790-792, 714/796, 714/786, 714/755, 375/265, 375/295, 375/298, 375/316, 375/279, 375/308, 375/329, 370/412, 370/465
• US Class Current: 714/792
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H04L 1/0003 by switching between different modulation schemes
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/0066 Parallel concatenated codes
• CPC Class Codes: H04L 1/0068 by puncturing
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/0075 Transmission of coding parameters to receiver H04L1/0023 takes precedence
• CPC Class Codes: H04L 2001/0097 Relays
• CPC Class Codes: H04L 27/3405 Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power

Abstract

16 QAM (Quadrature Amplitude Modulation) and 16 APSK (Asymmetric Phase Shift Keying) TTCM (Turbo Trellis Coded Modulation) with minimum bandwidth efficiency of 3 bit/s/Hz (bits per second per Hertz) using a rate 2/4 constituent encoder. Various encoder designs are presented that are operable to generate a signal whose modulation may vary as frequently as on a symbol by symbol basis while providing relatively very high throughput. Rate control sequences including RCs (Rate Controls), arranged in a period, govern the manner in which symbols of a signal are generated. The RCs correspond to various modulations that may each have a unique constellation and corresponding mapping. Different RCs may be included within a rate control sequence that correspond to 16 QAM, 16 APSK, QPSK (Quadrature Phase Shift Key), or even other modulation types. In addition, 1 or more uncoded bits may be used to generate the symbols of the coded signal.

Claims

1. A TTCM (Turbo Trellis Coded Modulation) encoder that encodes a plurality of input bits according to a rate control sequence, the encoder comprising:

a top interleaver operably coupled selectively to interleave at least some input bits of the plurality of input bits;

a top rate 2/4 constituent trellis encoder, communicatively coupled to the top interleaver and operable to receive selectively interleaved bits there from, that is operable to encode the selectively interleaved bits that have been interleaved by the top interleaver;

a bottom interleaver operably coupled selectively to interleave at least some input bits of the plurality of input bits;

a bottom rate 2/4 constituent trellis encoder, communicatively coupled to the bottom interleaver and operable to receive selectively interleaved bits there from, that is operable to encode the selectively interleaved bits that have been interleaved by the bottom interleaver;

a MUX (Multiplexor) that alternatively selects encoded bits that are output from the top rate 2/4 constituent trellis encoder and the bottom rate 2/4 constituent trellis encoder to produce a first plurality of multiplexed bits and a second plurality of multiplexed bits;

a puncturing functional block that is operable selectively to puncture the first plurality of multiplexed bits output from the MUX according to a first RC (Rate Control) of the rate control sequence to produce a first encoded symbol;

wherein the puncturing functional block is operable selectively to puncture the second plurality of multiplexed bits output from the MUX according to a second RC of the rate control sequence to produce a second encoded symbol;

a symbol mapper that maps the first encoded symbol according to the first RC thereby generating a first mapped symbol;

wherein the symbol mapper maps the second encoded symbol according to the second RC thereby generating a second mapped symbol;

wherein the first RC of the rate control sequence corresponds to a first modulation that includes a first mapping of either a first 16 QAM (Quadrature Amplitude Modulation) constellation or a first 16 APSK (16 Asymmetric Phase Shift Keying) constellation;

wherein the second RC of the rate control sequence corresponds to a second modulation that includes a second mapping of either a second 16 QAM constellation or a second 16 APSK constellation;

wherein the first mapped symbol and the second mapped symbol form an encoded signal; and

wherein the encoded signal has a bandwidth efficiency that is greater than approximately 3 bit/s/Hz (bits per second per Hertz).

2. The encoder of claim 1, further comprising:

a rate control sequencer that provides the first RC and the second RC of the rate control sequence to the puncturing functional block and to the symbol mapper.

3. The encoder of claim 1, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the plurality of RCs arranged in the period includes the first RC, a third RC, and the second RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation; and

the third RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation.

4. The encoder of claim 1, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the plurality of RCs arranged in the period includes the first RC, a third RC, and the second RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation; and

the third RC corresponds to a third modulation that includes a first mapping of a first QPSK (Quadrature Phase Shift Key) constellation.

5. The encoder of claim 1, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the plurality of RCs arranged in the period includes the first RC, a third RC, the second RC, and a fourth RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation;

the third RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation; and

the fourth RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation.

6. The encoder of claim 1, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation; and

the third RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation.

7. The encoder of claim 1, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the plurality of RCs arranged in the period includes the first RC, a third RC, and the second RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation; and

the third RC corresponds to a third modulation that includes a first mapping of a first QPSK (Quadrature Phase Shift Key) constellation.

8. The encoder of claim 1, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation;

the third RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation; and

the fourth RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation.

9. The encoder of claim 1, wherein:

the first encoded symbol includes 1 uncoded bit; and

the second encoded symbol includes 2 uncoded bits.

10. The encoder of claim 1, wherein:

the top interleaver operably coupled selectively to interleave at least some input bits of the plurality of input bits interleaves only odd positioned bits of the plurality of input bits; and

the bottom interleaver operably coupled selectively to interleave at least some input bits of the plurality of input bits interleaves only even positioned bits of the plurality of input bits.

11. The encoder of claim 1, wherein:

the first plurality of multiplexed bits output from the MUX according to the first RC of the rate control sequence includes 4 multiplexed bits;

the puncturing functional block selectively punctures 1 bit of the 4 multiplexed bits; and

the puncturing functional block employs the 3 non-punctured bits of the 4 multiplexed bits and 1 uncoded bit to produce the first encoded symbol.

12. The encoder of claim 1, wherein:

the second plurality of multiplexed bits output from the MUX according to the second RC of the rate control sequence includes 4 multiplexed bits;

the puncturing functional block selectively punctures 2 bits of the 4 multiplexed bits; and

the puncturing functional block employs the 2 non-punctured bits of the 4 multiplexed bits and 2 uncoded bits to produce the second encoded symbol.

13. The encoder of claim 1, wherein:

the top rate 2/4 constituent trellis encoder is implemented using 2 separate rate 2/4 constituent trellis encoders;

the first plurality of multiplexed bits output from the MUX according to the first RC of the rate control sequence includes 8 multiplexed bits;

the puncturing functional block selectively punctures 4 bits of the 8 multiplexed bits; and

the puncturing functional block employs the 4 non-punctured bits of the 8 multiplexed bits to produce the first encoded symbol.

14. The encoder of claim 1, wherein:

the bottom rate 2/4 constituent trellis encoder is implemented using 2 separate rate 2/4 constituent trellis encoders;

the second plurality of multiplexed bits output from the MUX according to the second RC of the rate control sequence includes 8 multiplexed bits;

the puncturing functional block selectively punctures 4 bits of the 8 multiplexed bits; and

the puncturing functional block employs the 4 non-punctured bits of the 8 multiplexed bits to produce the second encoded symbol.

15. The encoder of claim 1, wherein:

the encoder is implemented within a communication device; and

the communication device is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

16. A TTCM (Turbo Trellis Coded Modulation) encoding method that encodes a plurality of input bits according to a rate control sequence, the method comprising:

selectively interleaving at least some input bits of the plurality of input bits to generate a first plurality of selectively interleaved bits;

encoding the first plurality of selectively interleaved bits;

selectively interleaving at least some input bits of the plurality of input bits to generate a second plurality of selectively interleaved bits;

encoding the second plurality of selectively interleaved bits;

alternatively selecting encoded bits from the encoded first plurality of selectively interleaved bits and the encoded second plurality of selectively interleaved bits to produce a first plurality of multiplexed bits and a second plurality of multiplexed bits, respectively;

selectively puncturing the first plurality of multiplexed bits according to a first RC (Rate Control) of the rate control sequence to produce a first encoded symbol, wherein the first RC of the rate control sequence corresponds to a first modulation that includes a first mapping of either a first 16 QAM (Quadrature Amplitude Modulation) constellation or a first 16 APSK (16 Asymmetric Phase Shift Keying) constellation;

selectively puncturing the second plurality of multiplexed bits according to a second RC of the rate control sequence to produce a second encoded symbol, wherein the second RC of the rate control sequence corresponds to a second modulation that includes a second mapping of either a second 16 QAM constellation or a second 16 APSK constellation;

symbol mapping the first encoded symbol according to the first RC thereby generating a first mapped symbol;

symbol mapping the second encoded symbol according to the second RC thereby generating a second mapped symbol; and

forming an encoded signal using the first mapped symbol and the second mapped symbol, wherein the encoded signal has a bandwidth efficiency that is greater than approximately 3 bit/s/Hz (bits per second per Hertz).

17. The method of claim 16, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the plurality of RCs arranged in the period includes the first RC, a third RC, and the second RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation; and

the third RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation.

18. The method of claim 16, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the plurality of RCs arranged in the period includes the first RC, a third RC, and the second RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation; and

the third RC corresponds to a third modulation that includes a first mapping of a first QPSK (Quadrature Phase Shift Key) constellation.

19. The method of claim 16, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the plurality of RCs arranged in the period includes the first RC, a third RC, the second RC, and a fourth RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation;

the third RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation; and

the fourth RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation.

20. The method of claim 16, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation; and

the third RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation.

21. The method of claim 16, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the plurality of RCs arranged in the period includes the first RC, a third RC, and the second RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation; and

the third RC corresponds to a third modulation that includes a first mapping of a first QPSK (Quadrature Phase Shift Key) constellation.

22. The method of claim 16, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation;

the third RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation; and

the fourth RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation.

23. The method of claim 16, wherein:

the first encoded symbol includes 1 uncoded bit; and

the second encoded symbol includes 2 uncoded bits.

24. The method of claim 16, wherein:

the selectively interleaving of at least some input bits of the plurality of input bits includes interleaving only odd positioned bits of the plurality of input bits; and

the selectively interleaving of at least some input bits of the plurality of input bits includes interleaving only even positioned bits of the plurality of input bits.

25. The method of claim 16, wherein:

the first plurality of multiplexed bits according to the first RC of the rate control sequence includes 4 multiplexed bits;

the selectively puncturing includes puncturing 1 bit of the 4 multiplexed bits; and

employing the 3 non-punctured bits of the 4 multiplexed bits and 1 uncoded bit to produce the first encoded symbol.

26. The method of claim 16, wherein:

the second plurality of multiplexed bits according to the second RC of the rate control sequence includes 4 multiplexed bits;

the selectively puncturing includes puncturing 2 bits of the 4 multiplexed bits; and

employing the 2 non-punctured bits of the 4 multiplexed bits and 2 uncoded bits to produce the second encoded symbol.

27. The method of claim 16, wherein:

the first plurality of multiplexed bits according to the first RC of the rate control sequence includes 8 multiplexed bits;

the selectively puncturing includes puncturing 4 bits of the 8 multiplexed bits; and

employing the 4 non-punctured bits of the 8 multiplexed bits to produce the first encoded symbol.

28. The method of claim 16, wherein:

the second plurality of multiplexed bits according to the second RC of the rate control sequence includes 8 multiplexed bits;

the selectively puncturing includes puncturing 4 bits of the 8 multiplexed bits; and

employing the 4 non-punctured bits of the 8 multiplexed bits to produce the second encoded symbol.

29. The method of claim 16, wherein:

the method is performed within an encoder that is implemented within a communication device; and

the communication device is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

30. A TTCM (Turbo Trellis Coded Modulation) encoder that encodes a plurality of input bits according to a rate control sequence, the encoder comprising:

at least one constituent trellis encoder that is operable to encode the plurality of input bits thereby generating a first plurality of encoded bits and a second plurality of encoded bits;

a puncturing functional block that is operable selectively to puncture the first plurality of encoded bits according to a first RC (Rate Control) of the rate control sequence to produce a first encoded symbol;

wherein the puncturing functional block is operable selectively to puncture the second plurality of encoded bits according to a second RC of the rate control sequence to produce a second encoded symbol;

a symbol mapper that maps the first encoded symbol according to the first RC thereby generating a first mapped symbol;

wherein the symbol mapper maps the second encoded symbol according to the second RC thereby generating a second mapped symbol;

wherein the first RC of the rate control sequence corresponds to a first modulation that includes a first mapping of either a first 16 QAM (Quadrature Amplitude Modulation) constellation or a first 16 APSK (16 Asymmetric Phase Shift Keying) constellation;

wherein the second RC of the rate control sequence corresponds to a second modulation that includes a second mapping of either a second 16 QAM constellation or a second 16 APSK constellation;

wherein the first mapped symbol and the second mapped symbol form an encoded signal; and

wherein the encoded signal has a bandwidth efficiency that is greater than approximately 3 bit/s/Hz (bits per second per Hertz).

31. The encoder of claim 30, further comprising:

a rate control sequencer that provides the first RC and the second RC of the rate control sequence to the puncturing functional block and to the symbol mapper.

32. The encoder of claim 30, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the plurality of RCs arranged in the period includes the first RC, a third RC, and the second RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation; and

the third RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation.

33. The encoder of claim 30, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the plurality of RCs arranged in the period includes the first RC, a third RC, and the second RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation; and

the third RC corresponds to a third modulation that includes a first mapping of a first QPSK (Quadrature Phase Shift Key) constellation.

34. The encoder of claim 30, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the plurality of RCs arranged in the period includes the first RC, a third RC, the second RC, and a fourth RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation;

the third RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation; and

the fourth RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation.

35. The encoder of claim 30, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation; and

the third RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation.

36. The encoder of claim 30, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the plurality of RCs arranged in the period includes the first RC, a third RC, and the second RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation; and

the third RC corresponds to a third modulation that includes a first mapping of a first QPSK (Quadrature Phase Shift Key) constellation.

37. The encoder of claim 30, wherein:

the rate control sequence includes a plurality of RCs arranged in a period;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation;

the third RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation; and

the fourth RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation.

38. The encoder of claim 30, wherein:

the first encoded symbol includes 1 uncoded bit; and

the second encoded symbol includes 2 uncoded bits.

39. The encoder of claim 30, wherein:

the at least one constituent trellis encoder is a top rate 2/4 constituent trellis encoder;

the first plurality of encoded bits according to the first RC of the rate control sequence includes 4 encoded bits;

the puncturing functional block selectively punctures 1 bit of the 4 encoded bits; and

the puncturing functional block employs the 3 non-punctured bits of the 4 encoded bits and 1 uncoded bit to produce the first encoded symbol.

40. The encoder of claim 30, wherein:

the at least one constituent trellis encoder is a bottom rate 2/4 constituent trellis encoder;

the second plurality of encoded bits according to the second RC of the rate control sequence includes 4 encoded bits;

the puncturing functional block selectively punctures 2 bits of the 4 encoded bits; and

the puncturing functional block employs the 2 non-punctured bits of the 4 encoded bits and 2 uncoded bits to produce the second encoded symbol.

41. The encoder of claim 30, wherein:

the at least one constituent trellis encoder is a top rate 2/4 constituent trellis encoder that is implemented using 2 separate rate 2/4 constituent trellis encoders;

the first plurality of encoded bits according to the first RC of the rate control sequence includes 8 encoded bits;

the puncturing functional block selectively punctures 4 bits of the 8 encoded bits; and

the puncturing functional block employs the 4 non-punctured bits of the 8 encoded bits to produce the first encoded symbol.

42. The encoder of claim 30, wherein:

the at least one constituent trellis encoder is a bottom rate 2/4 constituent trellis encoder that is implemented using 2 separate rate 2/4 constituent trellis encoders;

the second plurality of encoded bits according to the second RC of the rate control sequence includes 8 encoded bits;

the puncturing functional block selectively punctures 4 bits of the 8 encoded bits; and

the puncturing functional block employs the 4 non-punctured bits of the 8 encoded bits to produce the second encoded symbol.

43. The encoder of claim 30, wherein:

the encoder is implemented within a communication device; and

the communication device is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

44. A TTCM (Turbo Trellis Coded Modulation) encoder that encodes a plurality of input bits according to a rate control sequence, the encoder comprising:

at least one constituent trellis encoder that is operable to encode the plurality of input bits thereby generating a first plurality of encoded bits, a second plurality of encoded bits, and a third plurality of encoded bits;

a puncturing functional block that is operable selectively to puncture the first plurality of encoded bits according to a first RC (Rate Control) of the rate control sequence to produce a first encoded symbol;

wherein the puncturing functional block is operable selectively to puncture the second plurality of encoded bits according to a second RC of the rate control sequence to produce a second encoded symbol;

wherein the puncturing functional block is operable selectively to puncture the third plurality of encoded bits according to a third RC of the rate control sequence to produce a third encoded symbol;

a symbol mapper that maps the first encoded symbol according to the first RC thereby generating a first mapped symbol;

wherein the symbol mapper maps the second encoded symbol according to the second RC thereby generating a second mapped symbol;

wherein the symbol mapper maps the third encoded symbol according to the third RC thereby generating a third mapped symbol;

wherein the first RC of the rate control sequence corresponds to a first modulation that includes a first mapping of either a first 16 QAM (Quadrature Amplitude Modulation) constellation or a first 16 APSK (16 Asymmetric Phase Shift Keying) constellation;

wherein the second RC of the rate control sequence corresponds to a second modulation that includes a second mapping of either a second 16 QAM constellation or a second 16 APSK constellation;

wherein the third RC of the rate control sequence corresponds to a third modulation that includes a first mapping of a first QPSK (Quadrature Phase Shift Key) constellation;

wherein the first mapped symbol, the second mapped symbol, and the third mapped symbol form an encoded signal; and

wherein the encoded signal has a bandwidth efficiency that is greater than approximately 3 bit/s/Hz (bits per second per Hertz).

45. The encoder of claim 44, further comprising:

a rate control sequencer that provides the first RC and the second RC of the rate control sequence to the puncturing functional block and to the symbol mapper.

46. The encoder of claim 44, wherein:

the rate control sequence includes 9 RCs arranged in a period;

the 9 RCs arranged in the period include the first RC, 7 occurrences of the second RC, and the third RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation; and

the third RC corresponds to the third modulation that includes the first mapping of the first QPSK constellation.

47. The encoder of claim 44, wherein:

the rate control sequence includes 9 RCs arranged in a period;

the 9 RCs arranged in the period include the first RC, 3 occurrences of the second RC, an additional occurrence of the first RC, 3 additional occurrences of the second RC, and the third RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation; and

the third RC corresponds to the third modulation that includes the first mapping of the first QPSK constellation.

48. The encoder of claim 44, wherein:

the rate control sequence includes 9 RCs arranged in a period;

the 9 RCs arranged in the period include 2 occurrences of the first RC, 2 occurrences of the second RC, 2 additional occurrences of the first RC, 2 additional occurrences of the second RC, and the third RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 QAM constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 QAM constellation; and

the third RC corresponds to the third modulation that includes the first mapping of the first QPSK constellation.

49. The encoder of claim 44, wherein:

the rate control sequence includes 9 RCs arranged in a period;

the 9 RCs arranged in the period include the first RC, 7 occurrences of the second RC, and the third RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation; and

the third RC corresponds to the third modulation that includes the first mapping of the first QPSK constellation.

50. The encoder of claim 44, wherein:

the rate control sequence includes 9 RCs arranged in a period;

the 9 RCs arranged in the period include the first RC, 3 occurrences of the second RC, an additional occurrence of the first RC, 3 additional occurrences of the second RC, and the third RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation; and

the third RC corresponds to the third modulation that includes the first mapping of the first QPSK constellation.

51. The encoder of claim 44, wherein:

the rate control sequence includes 9 RCs arranged in a period;

the 9 RCs arranged in the period include 2 occurrences of the first RC, 2 occurrences of the second RC, 2 additional occurrences of the first RC, 2 additional occurrences of the second RC, and the third RC;

the first RC corresponds to the first modulation that includes the first mapping of the first 16 APSK constellation;

the second RC corresponds to the second modulation that includes the second mapping of the second 16 APSK constellation; and

the third RC corresponds to the third modulation that includes the first mapping of the first QPSK constellation.

52. The encoder of claim 44, wherein:

the first encoded symbol includes 1 uncoded bit; and

the second encoded symbol includes 2 uncoded bits.

53. The encoder of claim 44, wherein:

the at least one constituent trellis encoder is a top rate 2/4 constituent trellis encoder;

the first plurality of encoded bits according to the first RC of the rate control sequence includes 4 encoded bits;

the puncturing functional block selectively punctures 1 bit of the 4 encoded bits; and

the puncturing functional block employs the 3 non-punctured bits of the 4 encoded bits and 1 uncoded bit to produce the first encoded symbol.

54. The encoder of claim 44, wherein:

the at least one constituent trellis encoder is a bottom rate 2/4 constituent trellis encoder;

the second plurality of encoded bits according to the second RC of the rate control sequence includes 4 encoded bits;

the puncturing functional block selectively punctures 2 bits of the 4 encoded bits; and

the puncturing functional block employs the 2 non-punctured bits of the 4 encoded bits and 2 uncoded bits to produce the second encoded symbol.

55. The encoder of claim 44, wherein:

the at least one constituent trellis encoder is a top rate 2/4 constituent trellis encoder that is implemented using 2 separate rate 2/4 constituent trellis encoders;

the first plurality of encoded bits according to the first RC of the rate control sequence includes 8 encoded bits;

the puncturing functional block selectively punctures 4 bits of the 8 encoded bits; and

the puncturing functional block employs the 4 non-punctured bits of the 8 encoded bits to produce the first encoded symbol.

56. The encoder of claim 44, wherein:

the at least one constituent trellis encoder is a bottom rate 2/4 constituent trellis encoder that is implemented using 2 separate rate 2/4 constituent trellis encoders;

the second plurality of encoded bits according to the second RC of the rate control sequence includes 8 encoded bits;

the puncturing functional block selectively punctures 4 bits of the 8 encoded bits; and

the puncturing functional block employs the 4 non-punctured bits of the 8 encoded bits to produce the second encoded symbol.

57. The encoder of claim 44, wherein:

the encoder is implemented within a communication device; and

the communication device is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.