Method of forming a conformal spacer adjacent to a gate electrode structure

• US 7,064,071 B2
• Filed: 03/30/2004
• Issued: 06/20/2006
• Est. Priority Date: 08/29/2003
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Schwan, Christoph
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US10/813,317
• Publication Number:
  US 20050048753A1
• Time in Patent Office: 812 Days
• Field of Search: 438/696, 438/305, 438/303, 438/306, 438/307
• US Class Current: 438/696
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

In a process for forming L-shaped sidewall spacers for a conducive line element, such as a gate electrode structure, the sacrificial spacers are formed of a material having a similar etch behavior as the material of the finally obtained L-shaped spacer, thereby improving tool utilization and reducing process complexity compared to conventional processes. In one particular embodiment, a spacer layer stack is provided having a first etch stop layer, a first spacer layer, a second etch stop layer, and a second spacer layer, wherein the first and second spacer layers are comprised of silicon nitride.

Claims

1. A method of forming spacer elements, the method comprising:

forming a conductive line above a semiconductor region;

conformally forming a spacer layer stack over said conductive line and said semiconductor region, said spacer layer stack comprising an etch stop layer separating a first spacer layer from a second spacer layer formed above said first spacer layer, said first and second spacer layers comprised of a material that may be etched selectively to said etch stop layer by a predefined etch chemistry;

anisotropically etching said second spacer layer to form sacrificial sidewall spacers;

removing portions of said etch stop layer that are exposed during the formation of said sacrificial sidewall spacers; and

removing said sacrificial sidewall spacers and exposed portions of said first spacer layer by an etch process using said specified etch chemistry to form said spacer elements, wherein the steps of anisotropically etching said second spacer layer to form sacrificial sidewall spacers, removing portions of said etch stop layer that are exposed during the formation of said sacrificial sidewall spacers, and removing said sacrificial sidewall spacers and exposed portions of said first spacer layer by a common etch process using said specified etch chemistry are all performed in a single etch chamber as an in situ process.

2. The method of claim 1, further comprising forming a second etch stop layer under said spacer layer stack.

3. The method of claim 2, wherein said second etch stop layer is comprised of the same material as said etch stop layer.

4. The method of claim 3, further comprising removing exposed portions of said second etch stop layer.

5. The method of claim 1, wherein said sacrificial sidewall spacers and exposed portions of said first spacer layer are removed by an isotropic etch process.

6. The method of claim 1, wherein said first and second spacer layers are comprised of substantially the same material.

7. The method of claim 6, wherein said first and second spacer layers are comprised of silicon nitride.

8. The method of claim 7, wherein said first and second spacer layers are formed by plasma enhanced chemical vapor deposition.

9. The method of claim 7, wherein said etch stop layer is comprised of silicon dioxide.

10. The method of claim 2, wherein said second etch stop layer is comprised of silicon dioxide.

11. The method of claim 5, further comprising controlling a degree of recessing said first spacer layer with respect to a top surface of said conductive line by correspondingly adjusting at least one process parameter of the isotropic etch process.

12. The method of claim 11, wherein said at least one process parameter represents at least one of an etch chemistry and an etch time.

13. The method of claim 1, further comprising adjusting a length of said conformal spacer element by controlling a thickness of said second spacer layer.

14. The method of claim 1, further comprising adjusting a thickness of said conformal spacer element by controlling a thickness of said first spacer layer.

15. The method of claim 1, wherein said conductive line represents a gate electrode of a field effect transistor receiving a lateral drain and source dopant profile that is controllable by the thickness and the length of said conformal spacer element.

16. The method of claim 1, wherein said sacrificial sidewall spacers are removed, at least partially, by an anisotropic etch process.

17. The method of claim 16, further comprising selecting a thickness of said etch stop layer on the basis of a height of said line and an etch selectivity of said anisotropic etch process.

18. The method of claim 17, wherein said exposed portions of said etch stop layer are removed, at least partially, during said anisotropic etch process.

19. A method of forming spacer elements, the method comprising:

forming a conductive line above a semiconductor region;

forming a spacer layer stack comprising a first etch stop layer formed of a first material, a first spacer layer formed of a second material, a second etch stop layer formed of said first material and a second spacer layer formed of said second material;

forming a sacrificial spacer at least from said second spacer layer; and

forming spacer elements at least from said first spacer layer by removing said sacrificial spacer, wherein the steps of forming sacrificial sidewall spacers and forming said conformal spacer elements by removing said sacrificial sidewall spacers are all performed in a single etch chamber as an in situ etch process.

20. The method of claim 19, wherein said second material comprises silicon nitride.

21. The method of claim 19, wherein said first material comprises silicon dioxide.

22. The method of claim 20, wherein said second material is deposited by plasma enhanced chemical vapor deposition.

23. The method of claim 19, wherein said sacrificial spacers are removed, at least partially, by an anisotropic etch process.

24. The method of claim 23, wherein said sacrificial spacers are substantially completely removed by an anisotropic etch process.

25. The method of claim 19, further comprising removing exposed portions of said first and second etch stop layers.

26. The method of claim 19, wherein said sacrificial sidewall spacers and exposed portions of said first spacer layer are removed by an isotropic etch process.

27. The method of claim 26, further comprising controlling a degree of recessing said first spacer layer with respect to a top surface of said conductive line by correspondingly adjusting at least one process parameter of said isotropic etch process.

28. The method of claim 27, wherein said at least one process parameter represents at least one of an etch chemistry and an etch time.

29. The method of claim 19, further comprising adjusting a length of said conformal spacer element by controlling a thickness of said second spacer layer.

30. The method of claim 26, further comprising adjusting a length of said conformal spacer element by controlling at least one process parameter of said isotropic etch process.

31. The method of claim 19, further comprising adjusting a thickness of said conformal spacer element by controlling a thickness of said first spacer layer.

32. The method of claim 19, wherein said conductive line represents a gate electrode of a field effect transistor receiving a lateral drain and source dopant profile that is controllable by a thickness and a length of said conformal spacer element.