Flash memory cell with buried floating gate and method for operating such a flash memory cell

• US 7,064,377 B2
• Filed: 03/24/2004
• Issued: 06/20/2006
• Est. Priority Date: 09/24/2001
• Status: Expired due to Fees

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Infineon Technologies AG
• Inventors: Langheinrich, Wolfram, Hagemeyer, Peter
• Primary Examiner(s): Pham, Long
• Application Number:
  US10/808,219
• Publication Number:
  US 20040228187A1
• Time in Patent Office: 818 Days
• Field of Search: 257/315, 257/314, 257/296
• US Class Current: 257/315
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench

Abstract

A programmable read-only memory cell and method of operating the programmable read-only memory cell. In one embodiment, the programmable read-only memory cell comprises a floating gate arranged in a trench, an epitaxial channel layer formed on the floating gate, the channel layer connecting a source electrode to a drain electrode, and a selection gate arranged above the channel line.

Claims

1. A programmable read-only memory cell, comprising:

a source electrode;

a drain electrode;

a channel layer formed between the source electrode and the drain electrode;

a floating gate isolated from the channel layer; and

a selection gate isolated from the channel layer, wherein the selection gate and the floating gate are arranged on opposite sides of the channel layer, and wherein a first insulator layer is arranged between the floating gate and the channel layer and a second insulator layer is arranged between the selection gate and the channel layer;

wherein the floating gate is arranged at least partly in a trench of a substrate, wherein the trench is formed between the source electrode and the drain electrode, and wherein the floating gate is electrically insulated from the substrate; and

wherein a trench capacitor is formed in the substrate, an inner electrode of said trench capacitor being formed by the floating gate and an outer electrode of said capacitor being formed by a first diffusion region.

2. The programmable read-only memory cell of claim 1, wherein the first diffusion region is formed within a second diffusion region and the second diffusion region is formed within a third diffusion region, the second diffusion region having a complementary doping with respect to the first diffusion region and with respect to the third diffusion region.

3. The programmable read-only memory cell of claim 1, wherein the first diffusion region of the read-only memory cell has an overlap region with one or more first diffusion regions of two read-only memory cells of a matrix-type arrangement of read-only memory cells that are directly adjacent in a direction perpendicular to a word line, and wherein the overlap region forms an electrically conductive connection between the first diffusion regions of a plurality of read-only memory cells in a series.

4. A programmable read-only memory cell, comprising:

a floating gate disposed in a trench of a substrate;

a channel layer formed over the floating gate, connecting a source electrode to a drain electrode;

a selection gate disposed above the channel layer;

a first insulator layer disposed between the floating gate and the channel layer;

a second insulator layer disposed between the selection gate and the channel layer;

an insulator layer disposed between the floating gate and the substrate; and

a trench capacitor, formed in the substrate, comprising an inner electrode formed by the floating gate and an outer electrode formed by a first diffusion region disposed between the insulator layer and the substrate.

5. The programmable read-only memory cell of claim 4, further comprising:

a second diffusion region surrounding the first diffusion region; and

a third diffusion region surrounding the second diffusion region, wherein the second diffusion region has a complementary doping with respect to the first diffusion region and with respect to the third diffusion region.

6. The programmable read-only memory cell of claim 5, wherein the first diffusion region has one or more overlap regions with one or more adjacent first diffusion regions of adjacent read-only memory cells in a direction perpendicular to a word line, and wherein the one or more overlap regions form an electrically conductive connection between adjacent first diffusion regions.

7. The programmable read-only memory cell of claim 5, wherein the channel layer is formed as an epitaxial layer having an n-type doping, and wherein the channel layer is isolated from the floating gate and the selection gate.

8. The programmable read-only memory cell of claim 5, wherein the source electrode and the drain electrode are formed at least partly on a surface of a substrate.