DMOS-transistor with lateral dopant gradient in drift region and method of producing the same
First Claim
Patent Images
1. A DMOS-transistor in a semiconductor body comprising:
- a trench in said semiconductor body bounded by a source-side wall, a drain-side wall, and a floor extending in a lateral direction between bottom ends of said walls; and
a drift region including a doped source-side wall region in said semiconductor body along said source-side wall, a doped drain-side wall region in said semiconductor body along said drain-side wall, and a doped floor region in said semiconductor body extending in said lateral direction along said floor;
wherein said floor region exhibits a dopant concentration gradient, in said lateral direction, of an implanted dopant that is implanted into said floor region to establish a higher dopant concentration in a first floor portion of said floor region and a lower dopant concentration in a second floor portion of said floor region.
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Abstract
A DMOS-transistor has a trench bordered by a drift region including two doped wall regions and a doped floor region extending along the walls and the floor of the trench. The laterally extending floor region has a dopant concentration gradient in the lateral direction. For example, the floor region includes at least two differently-doped floor portions successively in the lateral direction. This dopant gradient in the floor region is formed by carrying out at least one dopant implantation from above through the trench using at least one mask to expose a first area while covering a second area of the floor region.
90 Citations
30 Claims
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1. A DMOS-transistor in a semiconductor body comprising:
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a trench in said semiconductor body bounded by a source-side wall, a drain-side wall, and a floor extending in a lateral direction between bottom ends of said walls; and a drift region including a doped source-side wall region in said semiconductor body along said source-side wall, a doped drain-side wall region in said semiconductor body along said drain-side wall, and a doped floor region in said semiconductor body extending in said lateral direction along said floor; wherein said floor region exhibits a dopant concentration gradient, in said lateral direction, of an implanted dopant that is implanted into said floor region to establish a higher dopant concentration in a first floor portion of said floor region and a lower dopant concentration in a second floor portion of said floor region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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20. A DMOS-transistor in a semiconductor body comprising:
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a trench in said semiconductor body bounded by a source-side wall, a drain-side wall, and a floor extending in a lateral direction between bottom ends of said walls; and a drift region including a doped source-side wall region in said semiconductor body along said source-side wall, a doped drain-side wall region in said semiconductor body along said drain-side wall, and a doped floor region in said semiconductor body extending in said lateral direction along said floor; wherein said floor region exhibits a dopant concentration gradient, in said lateral direction, of an implanted dopant that is implanted into said floor region to establish a higher dopant concentration in a first floor portion of said floor region and a lower dopant concentration in a second floor portion of said floor region; wherein said semiconductor body comprises an insulating intermediate layer and a surface layer consisting of a semiconducting substrate disposed on said insulating intermediate layer, and wherein said DMOS-transistor is formed in and/or on said surface layer; further comprising, in said surface layer, a first well region of a first conductivity type, a second well region of a second conductivity type, a source region disposed within and surrounded by said first well region, a drain region of the second conductivity type disposed within and surrounded by said second well region; further comprising a gate region disposed on a surface of said surface layer of said semiconductor body, wherein said gate region, beginning from said source region, extends laterally over at least a portion of said trench over an entire lateral extension of said first well region; and wherein said floor region has a first concentration value of a total dopant concentration of a dopant of the second conductivity type therein, said source-side wall region has a second concentration value of a total dopant concentration of a dopant of the second conductivity type therein, and said drain-side wall region has a third concentration value of a total dopant concentration of a dopant of the second conductivity type therein. - View Dependent Claims (21)
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Specification