Electrostatic discharge protection structures having high holding current for latch-up immunity
First Claim
1. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:
- a silicon controlled rectifier (SCR), for coupling between a supply line of the IC and ground;
a first trigger device for coupling from the supply line to a first gate of the SCR;
a first shunt resistor for coupling between the first gate and ground;
a first gate control circuit, for coupling between the supply line and ground, and for further coupling to the first gate of the SCR; and
a common control circuit, for coupling between the supply line and ground, and for further coupling to the first gate control circuit.
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Accused Products
Abstract
An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.
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Citations
48 Claims
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1. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:
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a silicon controlled rectifier (SCR), for coupling between a supply line of the IC and ground; a first trigger device for coupling from the supply line to a first gate of the SCR; a first shunt resistor for coupling between the first gate and ground; a first gate control circuit, for coupling between the supply line and ground, and for further coupling to the first gate of the SCR; and a common control circuit, for coupling between the supply line and ground, and for further coupling to the first gate control circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:
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a silicon controlled rectifier (SCR), for coupling between a protected supply line of the IC and a ground; a first trigger device, for coupling from the said protected supply line to a first gate of the SCR; a first shunt resistor coupled between the first gate and ground; and an NMOS transistor having a drain and a source respectively coupled between the first gate and ground, said NMOS transistor having a gate for coupling to a supply line of the IC having a potential different from the potential of the protected supply line of the IC. - View Dependent Claims (10, 11)
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12. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:
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an SCR, having a respective GGNMOS transistor coupled to a first gate of said SCR, and a SGPMOS transistor coupled to a second gate of said SCR, said SCR, GGNMOS and SGPMOS transistors arranged in slices, further comprising; an N-well; a P-well positioned adjacent to said N-well and forming a junction therebetween; a first plurality of P+ regions interspersed in said N-well forming an anode of said SCR, for coupling to a protected supply line, and a source of said SGPMOS transistor; a first plurality of N+ regions interspersed in said P-well forming a cathode of said SCR, said first plurality of N+ regions for coupling to ground, and a source of said GGNMOS transistor, said first plurality of P+ and N+ regions being aligned and forming SCR and MOS transistor slices; a second plurality of N+ regions interspersed in said N-well between said first plurality of P+ regions and forming a plurality of second gates and coupled to said anode; a second plurality of P+ regions interspersed in said P-well between said first plurality of N+ regions and forming a plurality of first gates and coupled to said cathode; and a third plurality of P+ regions interspersed in said N-well and separated from said first plurality of P+ regions by a respective first plurality of perpendicular gate regions, said third plurality of P+ regions forming a drain of said SGPMOS transistor;
said first plurality of perpendicular gates coupled to said anode, said third plurality of P+ regions coupled to said cathode; anda third plurality of N+ regions interspersed in said P-well and separated from said second plurality of N+ regions by a respective second plurality of perpendicular gate regions, said third plurality of N+ regions forming a drain of said GGNMOS transistor;
said second plurality of perpendicular gates coupled to said cathode, said third plurality of N+ regions coupled to said anode.
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13. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:
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an N-well; a P-well positioned adjacent to said N-well and forming a junction therebetween; a first P+ region, forming a drain of a SGPMOS transistor disposed in said N-well, said first P+ region for coupling to ground; a second P+ region forming an emitter of a PNP transistor of an SCR and forming a source of SGPMOS disposed in said N-well and parallel to said first P+ region, said second P+ region for coupling to a supply line of the IC; a first gate region of said SGPMOS disposed parallel and between said first and second P+ regions, and over said N-well, said first gate region for coupling to the supply line of the IC; a first N+ region, forming the second gate of an SCR disposed in said N-well and parallel to said first and second P+ regions, said first N+ region for coupling to the supply line of the IC; a second N+ region forming an emitter of an NPN transistor of said SCR and forming a source of a GGNMOS disposed in said P-well, said second N+ region for coupling to ground; a third N+ region, forming a drain of a GGNMOS transistor disposed in said P-well parallel to said second N+ region, said third N+ region for coupling to the supply line of the IC; a second gate region disposed in parallel and between said second and third N+ regions, over said P-well, said gate region for coupling to ground; and a third P+ region, forming a second gate of the SCR disposed in said P-well and parallel to said second and third N+ regions, said third P+ region for coupling to ground.
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14. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:
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an SCR, having a respective GGNMOS transistor having a parasitic NPN transistor having a the base coupled to a first gate of said SCR, said SCR and GGNMOS transistor arranged in slices, further comprising; an N-well; a P-well, positioned adjacent to said N-well and forming a junction therebetween; a first plurality of P+ regions interspersed in said N-well, and forming an emitter of a PNP transistor of said SCR and adapted for coupling to a supply line of the IC; a first plurality of N+ regions interspersed in said N-well, and forming a drain contact region of said GGNMOS transistor, said first plurality of N+ regions for coupling to the supply line of the IC, a second N+ region, disposed over said junction of said N-well and P-well, and coupling to said first plurality of N+ regions and forming drain of said GGNMOS transistor; a third N+ region, forming an emitter of the NPN transistor and the source of said GGNMOS transistor, disposed in said P-well and parallel to said second N+ region, said third N+ region for coupling to ground; a gate region, disposed in parallel and between said second and third N+ regions, over said P-well, and for coupling to ground; a second P+ region, forming said first gate of said SCR, disposed in said P-well and parallel with said second and third N+ regions, said second P+ region for coupling to ground. - View Dependent Claims (15, 16, 17, 18)
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19. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:
an SCR having a respective GGNMOS transistor coupled to a first gate of said SCR, said SCR and GGNMOS transistor arranged in slices, further comprising; an N-well having interdigited fingers; a P-well having interdigited fingers, interlocking with said N-well fingers and forming a junction therebetween; a first plurality of P+ regions disposed in each of the interdigitated fingers of said N-well, and forming an emitter of a PNP transistor of said SCR, and adapted for coupling to a supply line of the IC, said; a first plurality of N+ regions disposed in each of the interdigitated fingers of said P-well and forming a drain of said GGNMOS transistor, said first plurality of N+ regions coupled to the supply line, a second N+ region disposed in said P-well and forming an emitter of the NPN transistor and the source of said GGNMOS transistor, said second N+ regions for coupling to ground; a gate region, disposed in parallel and between said first plurality of interspersed N+ regions and the second N+ region, over said P-well, and adapted for coupling to ground; a second P+ region, forming said first gate, disposed in said P-well and parallel with said second N+ region, and adapted for coupling to ground; and a plurality of third P+ regions disposed in each of the interdigitated fingers of said P-well and between said first plurality of P+ regions and said first plurality of N+ regions, each third P+ region coupled to the gate region forming a local substrate pick-up. - View Dependent Claims (20)
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21. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:
an SCR comprising a N-well; a P-well positioned adjacent to said N-well and forming a junction therebetween; a first plurality of P+ regions interspersed in said N-well forming an anode; a first plurality of N+ regions interspersed in said P-well forming a cathode and aligned with said first plurality of P+ regions, each said first N+ region and first P+ region having a first length in a range from 0.16 to 10 micrometers; a second plurality of P+ regions interspersed in said P-well between said first plurality of N+ regions and forming a plurality of first gates, a second plurality of N+ regions interspersed in said N-well between said first plurality of P+ regions and forming a plurality of second gates;
each said second N+ region and second P+ region having a second length in a range of 0.2 to 2 micrometers; andwherein a distance between the first P+ region and the second N+ region are in a range from 0.12 to 1.2 micrometers, and a distance between the first N+ region and the second P+ regions are in a range from 0.12 to 1.2 micrometers.
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22. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:
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a silicon controlled rectifier (SCR), for coupling between a first and a second supply line of the IC; a trigger device for coupling a gate of the SCR to one of said first and second supply lines; and a means for reducing an intrinsic resistance associated with said gate of the SCR. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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38. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:
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a silicon controlled rectifier (SCR), for coupling between a supply line of the IC and a ground line; a trigger device for coupling from the supply line to a second gate defined by an N-well of the SCR; an N-well resistor for coupling between the second gate and the supply line; and a shunt resistor for coupling between the second gate and the supply line, wherein said shunt resistor has a resistance value lower than the N-well resistor. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:
an SCR comprising an N-well; a P-well positioned adjacent to said N-well and forming a junction therebetween; a first elongated P+ region disposed parallel to said junction in said N-well, said first elongated P+ region forming an anode of said SCR; a first elongated N+ region disposed parallel to said junction and in said P-well, said first elongated N+ region forming a cathode of said SCR; a second elongated P+ region disposed parallel to said first elongated P+ region in said P-well, said second elongated P+ region forming a first gate of said SCR; a second elongated N+ region disposed parallel to said first elongated N+ region in said N-well, said second elongated N+ region forming a second gate of said SCR; and wherein a distance between the first elongated P+ region and the second elongated N+ region is in a range from 0.12 to 1.2 micrometers, and a distance between the first elongated N+ region and the second elongated P+ region is in a range from 0.12 to 1.2 micrometers.
Specification