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Integrated circuit with multiple spacer insulating region widths

  • US 7,064,396 B2
  • Filed: 03/01/2004
  • Issued: 06/20/2006
  • Est. Priority Date: 03/01/2004
  • Status: Active Grant
First Claim
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1. A method comprising:

  • providing a substrate;

    forming, over the substrate, a first gate for an N-channel transistor and a second gate for a P-channel transistor;

    forming a first sidewall spacer for the N-channel transistor lateral to the first gate and a second sidewall spacer for the P-channel transistor lateral to the second gate;

    forming a third sidewall spacer for the N-channel transistor lateral to the first sidewall spacer and a fourth sidewall spacer for the P-channel transistor lateral to the second sidewall spacer;

    providing a first mask over the first gate;

    implanting dopants, while the first mask is over the first gate, of a first conductivity type into the substrate;

    removing the first mask after the implanting the dopants of the first conductivity type;

    providing a second mask over the second gate;

    implanting dopants, while the second mask is over the second gate, of a second conductivity type into the substrate;

    removing the third sidewall spacer while the second mask is over the second gate;

    forming a first silicide region in the substrate for the N-channel transistor, wherein the first silicide region is substantially aligned with the first sidewall spacer; and

    forming a second silicide region in the substrate for the P-channel transistor, wherein the second silicide region is substantially aligned with the fourth sidewall spacer.

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