Integrated circuit with multiple spacer insulating region widths
First Claim
1. A method comprising:
- providing a substrate;
forming, over the substrate, a first gate for an N-channel transistor and a second gate for a P-channel transistor;
forming a first sidewall spacer for the N-channel transistor lateral to the first gate and a second sidewall spacer for the P-channel transistor lateral to the second gate;
forming a third sidewall spacer for the N-channel transistor lateral to the first sidewall spacer and a fourth sidewall spacer for the P-channel transistor lateral to the second sidewall spacer;
providing a first mask over the first gate;
implanting dopants, while the first mask is over the first gate, of a first conductivity type into the substrate;
removing the first mask after the implanting the dopants of the first conductivity type;
providing a second mask over the second gate;
implanting dopants, while the second mask is over the second gate, of a second conductivity type into the substrate;
removing the third sidewall spacer while the second mask is over the second gate;
forming a first silicide region in the substrate for the N-channel transistor, wherein the first silicide region is substantially aligned with the first sidewall spacer; and
forming a second silicide region in the substrate for the P-channel transistor, wherein the second silicide region is substantially aligned with the fourth sidewall spacer.
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Accused Products
Abstract
An integrated circuit with both P-channel transistors (823) and N-channel transistors (821) with different spacer insulating region widths. In one example, the outer sidewall spacer (321) of the N-channel transistors is removed while the P-channel regions (115) are masked such that the spacer insulating region widths of the N-channel transistors is less than the spacer insulating region widths of the P-channel transistors. Also, the drain/source silicide regions (805) of the N-channel transistors are located closer to the gates (117) of those transistors than the P-channel source/drain suicide regions (809) are located to the gates (119) of those transistors. Providing the P-channel transistors with greater spacer insulating widths and greater distances between the source/drain silicide regions and gates may increase the relative compressive stress of the channel region of the P-channel transistors relative the stress of the channel region of the N-channel transistors, thereby increasing the performance of the P-channel transistors.
32 Citations
15 Claims
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1. A method comprising:
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providing a substrate; forming, over the substrate, a first gate for an N-channel transistor and a second gate for a P-channel transistor; forming a first sidewall spacer for the N-channel transistor lateral to the first gate and a second sidewall spacer for the P-channel transistor lateral to the second gate; forming a third sidewall spacer for the N-channel transistor lateral to the first sidewall spacer and a fourth sidewall spacer for the P-channel transistor lateral to the second sidewall spacer; providing a first mask over the first gate; implanting dopants, while the first mask is over the first gate, of a first conductivity type into the substrate; removing the first mask after the implanting the dopants of the first conductivity type; providing a second mask over the second gate; implanting dopants, while the second mask is over the second gate, of a second conductivity type into the substrate; removing the third sidewall spacer while the second mask is over the second gate; forming a first silicide region in the substrate for the N-channel transistor, wherein the first silicide region is substantially aligned with the first sidewall spacer; and forming a second silicide region in the substrate for the P-channel transistor, wherein the second silicide region is substantially aligned with the fourth sidewall spacer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification