Electronic package with integrated capacitor

• US 7,064,412 B2
• Filed: 01/25/2000
• Issued: 06/20/2006
• Est. Priority Date: 01/25/2000
• Status: Expired due to Fees

• Current Assignee: 3M Innovative Properties Company (3M Company)
• Original Assignee: 3M Innovative Properties Company (3M Company)
• Inventors: Harvey, Paul M., Kieschke, Robert R., Geissinger, John D.
• Primary Examiner(s): RICHARDS, NORMAN DREW
• Application Number:
  US09/491,302
• Publication Number:
  US 20030015787A1
• Time in Patent Office: 2,338 Days
• Field of Search: 257/532, 257/386, 257/552, 257/535
• US Class Current: 257/535
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/0101 Neon [Ne]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

An electronic package including a conductive trace layer having a first side and a second side. The conductive trace layer is patterned to define a plurality of interconnect pads. A flexible dielectric substrate is mounted on the first side of the conductive trace layer. A flexible capacitor including a first conductive layer, a second conductive layer and a layer of dielectric material disposed between the first and the second conductive layers is mounted with the first conductive layer adjacent to the second side of the conductive trace layer. A plurality of interconnect regions extend through the first conductive layer and the dielectric material layer of the capacitor. An interconnect member is connected between each one of the conductive layers of the capacitor and a corresponding set of the interconnect pads. The first conductive layer of the capacitor is electrically connected to a first set of the interconnect pads and the second conductive layer of the capacitor is electrically connected to a second set of the interconnect pads. The interconnect members corresponding to the second set of interconnect pads extend through one of the interconnect regions. An aperture extends through the dielectric substrate adjacent to each one of the interconnect pads. A stiffening member is mounted adjacent to the second conductive layer of the capacitor. A device receiving region is formed through the dielectric substrate, the conductive trace layer and the capacitor.

Claims

1. An electronic package, comprising:

a conductive trace layer having a first side and a second side, the conductive trace layer being patterned to define a piurality of interconnect pads;

a dielectric substrate mounted on the first side of the conductive trace layer;

an embedded capacitor having a capacitance of from about 1 nF/sq.cm. to about 100 nF/sq.cm., including a first conductive layer, a second conductive layer and a layer of dielectric material made of a non-conductive polymer blended with high dielectric constant particles disposed between the first and the second conductive layers, the first conductive layer attached to the second side of the conductive trace layer by a first adhesive layer;

a plurality of interconnect regions extending through the first conductive layer and the dielectric material layer of the capacitor; and

an interconnect member connected between each of the conductive layers of the capacitor and a corresponding set of the interconnect pads, the first conductive layer of the capacitor being electrically connected to a first set of the interconnect pads and the second conductive layer of the capacitor being electrically connected to a second set of the interconnect pads, the interconnect members corresponding to the second set of interconnect pads extending through one of the interconnect regions.

2. The electronic package of claim 1 wherein the first electrode is maintained at a first reference voltage and wherein the second electrode is maintained at a second reference voltage different from the first reference voltage.

3. The electronic package of claim 1 further comprising an electrically conductive stiffening member attached to the second conductive layer of the capacitor by a second adhesive layer.

4. The electronic package of claim 3 further comprising a device receiving region extending through the dielectric substrate, the conductive trace layer and the capacitor, and further comprising an electronic device attached to the device receiving region on the stiffening member by a third adhesive layer.

5. The electronic package of claim 1 wherein the capacitor has a capacitance of from about 2 nF/sq. cm. to about 30 nE/sq. cm.

6. The electronic package of claim 1 wherein the capacitor has a capacitance of from about 5 nF/sq. cm. to about 15 nE/sq. cm.

7. The electronic package of claim 1 wherein the capacitor has a capacitance of at least 30 nF/sq. cm.

8. The electronic package of claim 1 wherein die dielectric material of the capacitor has a thickness of from about 0.5 um to about 30 um.

9. The electronic package of claim 1 wherein the dielectric material of the capacitor includes a metal oxide.

10. The electronic package of claim 1 wherein the dielectric constant particles are formed from a material selected from the group consisting of barium titanate, barium strontium titanate, titanium oxide, lead zirconium titanate and tantalum oxide.

12. The electronic package of claim 1 wherein the dielectric substrate includes a polymeric film.

13. The electronic package of claim 12 wherein said polymeric film is polyimide film.

14. The electronic package of claim 1 wherein the interconnect member is a solder plug.

15. The electronic package of claim 1 wherein each interconnect pad is a solderball pad.

16. The electronic package of claim 15 Wherein the dielectric substrate has an aperture extending therethrough adjacent to each solderbail pad.

11. The electronic package of eiaim 1 wherein the dielectric substrate includes a plurality of apertures, each one of the apertures being positioned adjacent to one of the interconnect region of the capacitor.