Method and structure of diode

• US 7,064,418 B2
• Filed: 02/20/2004
• Issued: 06/20/2006
• Est. Priority Date: 02/21/2003
• Status: Active Grant

• Current Assignee: InnoLux Corporation
• Original Assignee: Toppoly Optoelectronics Corporation (InnoLux Corporation)
• Inventors: Ker, Ming-Dou, Yang, Sheng-Chieh, Deng, Chih-Kang, Shih, An, Li, Ying-Hsin, Tseng, Tang-Kui
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US10/781,879
• Publication Number:
  US 20040164381A1
• Time in Patent Office: 851 Days
• Field of Search: 257/656, 257/355
• US Class Current: 257/656
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells

Abstract

A method and a structure of a diode are provided. The diode is used in an electrostatic discharge protection circuit using TFT (Thin Film Transistor) fabrication technology. A semiconductor layer is formed on a substrate. A first region of a first carrier concentration is formed in the semiconductor layer. A second region of a second carrier concentration is formed in the semiconductor layer. An insulator is formed on the semiconductor layer. The insulator layer is etched to form at least a contact window. The contact window exposes a portion of an upper surface of the semiconductor layer. A metal layer is formed on the insulator layer. The metal layer fills up the contact window to contact the semiconductor layer.

Claims

1. A method of fabricating a diode on a substrate, said method comprising:

forming a semiconductor layer on said substrate;

forming a first region of a first carrier concentration in said semiconductor layer;

forming a second region of a second carrier concentration in said semiconductor layer;

forming a third region of a third carrier concentration in said semiconductor layer, said third carrier concentration is of a first conductivity type and is smaller than said first carrier concentration, said first region separates from said second region, said third region locates between said first region and said second region, said third region is adjacent to said first region;

forming a fourth region of a fourth carrier concentration in said semiconductor layer, said fourth carrier concentration is of a second conductivity type and is smaller than said second carrier concentration, said third region separates from said second region, said fourth region locates between said third region and said second region, said fourth region is adjacent to said second region;

forming a fifth region of a fifth carrier concentration in said semiconductor layer, wherein said fifth carrier concentration is of said first conductivity type and is smaller than said third carrier concentration, said third region separates from said fourth region, said fifth region locates between said third region and said fourth region;

forming an insulator layer on said semiconductor layer;

etching said insulator layer to form at least a contact window; and

forming a metal layer on said insulator layer;

wherein said contact window exposes a portion of an upper surface of said semiconductor layer, said metal layer fills up said contact window to contact said semiconductor layer.

2. The method of claim 1, wherein said diode is formed by a thin-film transistor process, and said diode is applied to a circuit.

3. The method of claim 1, wherein said second conductivity type is a negative type if said first conductivity type is a positive type, said second conductivity type is a positive type if said first conductivity type is a negative type.

4. A diode, comprising:

a semiconductor layer, comprising;

a first region of a first carrier concentration, wherein said first carrier concentration is of a first conductivity type;

a second region of a second carrier concentration, wherein said second carrier concentration is of a second conductivity type;

a third region of a third carrier concentration, wherein said third carrier concentration is of said first conductivity type and is smaller than said first carrier concentration, said first region separates from said second region, said third region locates between said first region and said second region, said third region is adjacent to said first region;

a fourth region of a fourth carrier concentration, wherein said fourth carrier concentration is of said second conductivity type and is smaller than said second carrier concentration, said third region separates from said second region, said fourth region locates between said third region and said second region; and

said fourth region is adjacent to said second region;

a fifth region of a fifth carrier concentration, wherein said fifth carrier concentration is of said first conductivity type and is smaller than said third carrier concentration, said third region separates from said fourth region, said fifth region locates between said third region and said fourth region;

an insulator layer disposed on said semiconductor layer, said insulator layer including at least a contact window; and

a metal layer disposed on said insulator layer;

wherein said contact window exposes a portion of an upper surface of said semiconductor layer, said metal layer fills up said contact window to contact said semiconductor layer.

5. The diode of claim 4, wherein said diode is formed by a thin-film transistor process, said diode is applied to a circuit.

6. The diode of claim 4, wherein said second conductivity type is a negative type if said first conductivity type is a positive type, said second conductivity type is a positive type if said first conductivity type is a negative type.

7. An electrostatic discharge protection circuit, comprising a diode as described in claim 4.