Integrated circuit package device

• US 7,064,442 B1
• Filed: 07/02/2003
• Issued: 06/20/2006
• Est. Priority Date: 07/02/2003
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Lane, William A., Moore, Tom D., O'Byrne, Nicola M., O'Neill, Mike A., Reidy, John R., McHugh, Leo P.
• Primary Examiner(s): ANDUJAR, LEONARDO
• Application Number:
  US10/612,274
• Time in Patent Office: 1,084 Days
• Field of Search: 361/268, 361/603, 361/620, 361/623, 361/836, 361666-677, 257/666, 257/670, 257/676, 257/734, 257/773, 257/776
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/495 Lead-frames or other flat leads H01L23/498 takes precedence; lead frame interconnections between components H01L23/52
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The invention relates to integrated circuit package devices including at least two component chips. In particular the invention describes such devices having a transformer provided between the two components chips, the transformer providing isolation between the component chips and wherein the total assembly is sufficiently small that it can be integrated in standard IC packages.

Claims

1. A package device having a patterned lead frame with at least two isolated patterned dies mounted thereon, the package device additionally having a planar transformer component, the planar transformer component comprising at least two planar transformers, each being individually mounted to the lead frame between the at least two patterned dies, the transformers adapted to provide for the selective coupling of energy between the two dies.

2. The device as claimed in claim 1 wherein the selective coupling effects a rejection of some of the unwanted energy components so as to provide for a blocking of predefined component signals from coupling between the isolated patterned dies.

3. The device as claimed in claim 1 wherein the coupled energy is in the form of a power signal such that the coupling between the two dies is used to provide or share power between the two dies.

4. The device as claimed in claim 1 wherein the coupled energy is in the form of a communication signal such that a coupling of the energy effects a transfer of information between the two dies.

5. The device as claimed in claim 1 wherein the transformer component is formed as a planar transformer in a substrate, the substrate being mounted to the lead frame.

6. The device as claimed in claim 1 wherein the transformer component is a planar transformer and is formed using wafer level fabrication technology such as is used for forming redistribution layers in bumped chips.

7. The device as claimed in claim 6 wherein the transformer is fabricated on either a glass or silicon substrate which is then mounted to the lead frame.

8. The device as claimed in claim 1 wherein the transformer component is a discrete micro-miniaturized transformer.

9. The device as claimed in claim 8 wherein the micro-miniaturised transformer is fabricated using MEMS technology.

10. The device as claimed in claim 1 wherein the transformer component is coupled directly onto heat sinks of the lead frame, thereby providing for a reduction of thermal impedance within the package device.

11. The device as claimed in claim 1 wherein the substrate on which the transformer is formed is a flexible substrate.

12. The device as claimed in claim 11 wherein the flexible substrate is made from a polyimide material.

13. The device as claimed in any of claims 12 wherein legs of the lead frame define an axis and the selective coupling of energy will, when it occurs, occur in a direction perpendicular to said axis.

14. The device as claimed in any of claims 12 wherein legs of the lead frame define an axis and the selective coupling of energy will, when it occurs, occur in a direction parallel to said axis.

15. The device of claim 1 wherein the transformers provide multiple channels of communication between the dies.

16. An integrated multi-chip package device comprising a first chip, a second chip and a planar isolating transformer component provided between the first and second chip, the first chip, the second chip and the planar transformer component being formed of two planar transformers on segmented portions of the lead frame of the package device.

17. The package device as claimed in claim 16 wherein the coupling of signals across the first and second chips via the transformer component is configured in a north-south configuration.

18. The package device as claimed in claim 16 wherein the coupling of signals across the first and second chips via the transformer component is configured in an east-west configuration.

19. A method of isolating components provided on a packaged multi-die device, the method comprising the steps of:

a) providing a patterned lead frame,

b) mounting on the lead frame a plurality of patterned dies, and

c) coupling energy between at least two of the patterned dies via at least two planar isolating transformers, the planar isolating transformers being provided on a separate component within the package to the dies being coupled.