Coarse tuning for fractional-N synthesizers

• US 7,064,591 B1
• Filed: 07/29/2004
• Issued: 06/20/2006
• Est. Priority Date: 05/11/2004
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Bunch, Ryan, Humphreys, Scott
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US10/901,669
• Time in Patent Office: 691 Days
• Field of Search: None
• US Class Current: 327/156
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 7/103 the additional signal being a digital signal
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
• CPC Class Codes: H03L 7/1974 for fractional frequency division

Abstract

An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer such that the phase lock loop operates in an integer division mode during coarse tuning, thereby eliminating jitter due to fractional-N operation during coarse tuning. The coarse tuning circuit includes divide value generation circuitry that provides an integer divide value to an N divider of the PLL during coarse tuning and a fractional-N sequence to the N divider during fractional-N operation.

Claims

1. A fractional-N frequency synthesizer comprising:

a phase lock loop (PLL); and

coarse tuning circuitry coupled to the PLL and adapted to control the PLL such that the PLL operates in an integer division mode during coarse tuning and a fractional-N division mode during normal operation, wherein the coarse tuning circuitry comprises divide value generation circuitry adapted to;

provide an integer divide value to a divider of the PLL when operating in the integer division mode; and

provide a fractional sequence of divide values to the divider of the PLL when operating in the fractional-N division mode,

wherein the PLL comprises a controlled oscillator (CO) and the coarse tuning circuitry further comprises;

an M divider adapted to divide a reference signal from the PLL by a factor M to provide an divided reference signal; and

tuning logic adapted to;

compare a frequency of the divided reference signal and a frequency of a divided controlled oscillator (CO) signal during coarse tuning, wherein the divided CO signal is a CO signal from the CO divided by the integer divide value; and

provide a tuning curve control signal to select a tuning curve for a CO of the PLL based thereon to effect coarse tuning of the CO.

2. The frequency synthesizer of claim 1 wherein the tuning logic is further adapted to compare the frequency of the divided reference signal and the frequency of the divided CO signal by comparing the period of the divided reference frequency with the period of the divided CO frequency.

3. The frequency synthesizer of claim 2 further comprising synchronization circuitry adapted to synchronize the M divider and an N divider of the PLL based on an output signal of the CO, thereby improving the accuracy of the comparison of the frequency of the divided reference signal and the frequency of the divided CO signal.

4. The fractional-N frequency synthesizer of claim 1 wherein the integer divide value is an integer component of a product of the multiplication of a desired divide value of the fractional-N synthesizer and the factor M.

5. The circuit of claim 4 wherein divide value generation circuitry multiplies the desired divide value of the fractional-N synthesizer and the factor M by left shifting the bits of the desired divide value by log₂(M) bits.

6. The fractional-N frequency synthesizer of claim 1 wherein the tuning logic is further adapted to provide a control signal to the divide value generation circuitry, thereby controlling the mode of operation of the divide value generation circuitry.

7. The fractional-N frequency synthesizer of claim 1 wherein the CO comprises a circuit having a selectable capacitance with a plurality of settings corresponding to a plurality of tuning curves and the tuning logic is further adapted to provide the tuning curve control signal to sequentially select the plurality of tuning curves until the frequency of the divided CO signal is within a desired proximity of the frequency of the divided reference signal.

8. The fractional-N frequency synthesizer of claim 1 wherein the CO comprises a circuit having a plurality of selectable elements corresponding to a plurality of tuning curves and the tuning logic is further adapted to provide the tuning curve control signal to sequentially select the plurality of tuning curves until the frequency of the divided CO signal is within a desired proximity of the frequency of the divided reference signal.

9. The fractional-N frequency synthesizer of claim 7 wherein the coarse tuning circuitry further comprises a coarse tune counter adapted to receive the tuning curve control signal and generate a select signal to provide to the circuit of the CO to control the selectable capacitance.

10. The frequency synthesizer of claim 9 wherein the CO and the coarse tune counter are implemented in one of the group consisting of an integrated circuit and a semiconductor die.

11. The frequency synthesizer of claim 1 wherein the coarse tuning circuitry further comprises a switch for coupling a fixed initialization signal to a fine tuning signal for the CO to override feedback from a phase detector of the PLL during coarse tuning and bias the CO to operate at a predefined control setting.

12. The frequency synthesizer of claim 11 wherein the tuning logic is further adapted to control thc switch.

13. The frequency synthesizer of claim 1 wherein the CO comprises a circuit having a selectable capacitance with a plurality of settings corresponding to a plurality of tuning curves and the tuning logic is further adapted to provide the tuning curve control signal to sequentially decrement the selectable capacitance to select another of the plurality of tuning curves when the divided CO signal has a frequency less than that of the divided reference signal.

14. The frequency synthesizer of claim 13 wherein the circuit of the CO is initialized to one of the tuning curves associated with a lowest acceptable operating frequency range.

15. The frequency synthesizer of claim 1 wherein the CO comprises a circuit having a selectable capacitance with a plurality of settings corresponding to a plurality of tuning curves and the tuning logic is further adapted to provide the tuning curve control signal to sequentially increment the selectable capacitance to select another of the plurality of tuning curves when the divided CO signal has a frequency greater than that of the divided reference signal.

16. The frequency synthesizer of claim 15 wherein the circuit of the CO is initialized to one of the tuning curves associated with a highest acceptable operating frequency range.

17. A method for coarse tuning a fractional-N frequency synthesizer comprising:

providing an integer divide value to a divider of a phase lock loop (PLL) during coarse tuning, thereby controlling the PLL such that the PLL operates in an integer division mode during coarse tuning;

providing a fractional sequence of divide values to the divider of the PLL during normal operation, thereby controlling the PLL such that the PLL operates in a fractional-N division mode during normal operation;

dividing a reference signal from the PLL by a factor M to provide a divided reference signal;

comparing a frequency of the divided reference signal and a frequency of a divided controlled oscillator (CO) signal during coarse tuning, wherein the divided CO signal is a CO signal from a CO of the PLL divided by the integer divide value; and

providing a tuning curve control signal to select a tuning curve for the CO of the PLL based thereon to effect coarse tuning of the CO.

18. The method of claim 17 wherein the CO comprises a circuit having a selectable capacitance with a plurality of settings corresponding to a plurality of tuning curves, and the method further comprises providing the tuning curve control signal to sequentially decrement the selectable capacitance to select another of tie plurality of tuning curves when the divided CO signal has a frequency less than that of the divided reference signal.

19. The method of claim 18 further comprising initializing the circuit of the CO to one of the tuning curves associated with a lowest acceptable operating frequency range.

20. The method of claim 17 wherein the CO comprises a circuit having a selectable capacitance with a plurality of settings corresponding to a plurality of tuning curves, and the method further comprises providing the tuning curve control signal to sequentially increment the selectable capacitance to select another of the plurality of tuning curves when the divided CO signal has a frequency greater than that of the divided reference signal.

21. The method of claim 20 further comprising initializing the circuit of the CO to one of the tuning curves associated with a highest acceptable operating frequency range.

22. The method of claim 17 wherein the comparing step is based on comparing the period of the divided reference frequency with the period of the divided CO frequency.

23. The method of claim 22 further comprising synchronizing the dividing the reference signal by a factor of M step and the division of the CO signal based on the CO output signal, thereby improving the accuracy of the comparison of the frequency of the divided reference signal and the frequency of the divided CO signal.

24. The method of claim 17 further comprising coupling a fixed initialization signal to a fine tuning signal for the CO to override feedback from a phase detector of the PLL during coarse tuning and bias the CO to operate at a predefined control setting.

25. The method of claim 17 wherein the CO comprises a circuit having a selectable capacitance with a plurality of settings corresponding to a plurality of tuning curves, and the method further comprises providing the tuning curve control signal to sequentially select the plurality of tuning curves until the frequency of the divided CO signal is within a desired proximity of the frequency of the divided reference signal.

26. The method of claim 17 wherein the CO comprises a circuit having a plurality of selectable elements corresponding to a plurality of tuning curves, and the method further comprises providing the tuning curve control signal to sequentially select the plurality of tuning curves until the frequency of the divided CO signal is within a desired proximity of the frequency of the divided reference signal.

27. A method for coarse tuning a fractional-N frequency synthesizer comprising:

providing an integer divide value to a divider of a phase lock loon (PLL) during coarse tuning thereby controlling the PLL such that the PLL operates in an integer division mode during coarse tuning;

providing a fractional sequence of divide values to the divider of the PLL during normal operation, thereby controlling the PLL such that the PLL operates in a fractional-N division mode during normal operation; and

determining the integer divide value based on the multiplication of a desired divide value of the fractional-N synthesizer and the factor M.

28. The method of claim 27 wherein the integer divide value is an integer component of the product of the desired divide value of the fractional-N synthesizer and the factor M.

29. The method of claim 27 wherein the multiplication of the desired divide value of the fractional-N synthesizer and the factor M is based on left shifting the bits of the desired divide value by log₂(M) bits.

30. A circuit for coarse tuning a fractional-N frequency synthesizer comprising:

a) divide value generation circuitry adapted to provide an integer divide value to a divider of a phase lock loop (PLL) when operating in an integer mode, and further adapted to provide a fractional sequence of divide values to the divider of the PLL when operating in a fractional-N mode, the mode of the divide value generation circuitry selected by a control signal;

b) an M divider adapted to divide a reference signal from the PLL by a factor M to provide an divided reference signal; and

c) tuning logic adapted to;

i) provide the control signal such that the divide value generation circuitry operates in the integer mode during coarse tuning and in the fractional-N mode thereafter; and

during coarse tuning, further adapted to;

ii) compare a frequency of the divided reference signal and a frequency of a divided controlled oscillator (CO) signal during coarse tuning, wherein the divided CO signal is a CO signal from a CO of the PLL divided by the integer divide value; and

iii) provide a tuning curve control signal to select a tuning curve for the CO based thereon to effect coarse tuning of the CO.

31. The circuit of claim 30 wherein the integer divide value is an integer component of a product of the multiplication of a desired divide value of the fractional-N synthesizer and the factor M.

32. The circuit of claim 31 wherein divide value generation circuitry multiplies the desired divide value of the fractional-N synthesizer and the factor M by left shifting the bits of the desired divide value by log₂(M) bits.