Multi-camera system for implementing digital slow shutter video processing using shared video memory

• US 7,064,778 B1
• Filed: 09/08/2000
• Issued: 06/20/2006
• Est. Priority Date: 09/10/1999
• Status: Expired due to Term

• Current Assignee: Pelco (Schneider Electric SE)
• Original Assignee: Pelco (Schneider Electric SE)
• Inventors: Waehner, Glenn C.
• Primary Examiner(s): Vu, Ngoc-Yen
• Assistant Examiner(s): Hannett, James M.
• Application Number:
  US09/658,177
• Time in Patent Office: 2,111 Days
• Field of Search: 348/211.5, 348/211.11, 348/211.1, 348/434.1, 348/435.1, 348/495, 348/423.1
• US Class Current: 348/211.11
• CPC Class Codes: H04N 21/4147 PVR [Personal Video Recorder] H04N5/76 takes precedence ; arrangements for broadcast with accumulation-type receivers H04H20/40
• CPC Class Codes: H04N 21/4223 Cameras H04N23/00 takes precedence
• CPC Class Codes: H04N 21/43622 Interfacing an external recording device
• CPC Class Codes: H04N 21/440281 by altering the temporal resolution, e.g. by frame skipping television signal recording using magnetic recording on tape for reproducing at a rate different from the recording rate H04N5/783
• CPC Class Codes: H04N 23/66 Remote control of cameras or camera parts, e.g. by remote control devices
• CPC Class Codes: H04N 23/90 Arrangement of cameras or camera modules, e.g. multiple cameras in TV studios or sports stadiums
• CPC Class Codes: H04N 5/268 Signal distribution or switching
• CPC Class Codes: H04N 5/76 Television signal recording
• CPC Class Codes: H04N 5/77 between a recording apparatus and a television camera
• CPC Class Codes: H04N 5/915 for field- or frame-skip recording or reproducing

Abstract

A technique, specifically a method and apparatus that implements the method, that allows a memory to be located remotely from a video source. Specifically, the method provides a write control signal between a video source and a remote memory that allows the remote memory to provide a video image during slow-shutter operation of the camera.

Claims

1. A closed circuit video system that utilizes shared video memory, said system having:

a plurality, N, of image capture devices each producing a corresponding video signal so as to define a plurality of N video signals;

a circuit, responsive to said plurality of video signals, which in response to a selection control signal, routes a specific group, M, of selected ones of said video signals produced by M respective ones of the N image capture devices to associated output devices, where M and N are positive integers; and

wherein said circuit comprises;

a separate memory for each one of said M video signals, said separate memory implements a multi-functional shared store for its associated one of the M image capture devices, through which said separate memory supports video processing functionality associated with standard shutter imaging and slow shutter imaging as well as video processing functionality for other operations provided through said circuit such that said separate memory eliminates a need to have a separate frame store situated within or proximate to said associated one image capture device to implement slow shutter imaging, wherein, during standard shutter imaging and slow shutter imaging, the separate memory is updated at a field rate appropriate to said associated one image capture device and read out at a rate appropriate to an image store function; and

said separate memory communicatively interacts with said associated one image capture device through which said associated one image capture device specifies, in response to whether said associated one image capture device is functioning in said standard or slow shutter imaging, if the separate memory should then update its video contents or not in response to a corresponding one of the video signals then being produced by said associated one image capture device.

2. The system recited in claim 1 wherein the circuit comprises a frame grabber, an N×

M video recording multiplexer, an N×

M video matrix switch or an N×

M video selector.

3. The system recited in claim 2 wherein said associated one image capture device comprises a video camera or any other device that produces a video source signal.

4. The system recited in claim 2 wherein said communicative interaction between said associated one image capture device and said separate memory occurs through bi-directional signaling there between.

5. The system recited in claim 4 wherein said separate memory comprises a dual-ported memory.

6. The system recited in claim 4 wherein said output devices comprise a plurality of video monitors.

7. The system recited in claim 6 wherein said output devices include at least one video recorder.

8. The system recited in claim 4 wherein the circuit synchronizes capture and refresh display of images from said one video signal produced by said associated one of the image capture devices when said associated one image capture device is operating in a slow shutter image processing mode.

9. The system recited in claim 4 wherein the bidirectional signaling comprises a write control signal produced by said associated one image capture device, wherein the write control signal is a don'"'"'t write signal.

10. The system recited in claim 9 wherein said associated one image capture device comprises a video camera or any other device that produces a video source signal.

11. The system recited in claim 9 wherein said separate memory comprises a dual-ported memory.

12. The system recited in claim 9 wherein said output devices comprise a plurality of video monitors.

13. The system recited in claim 12 wherein said output devices further comprise at least one video recorder.

14. The system recited in claim 9 wherein the bidirectional signaling further comprises an enable-slow-shutter signal to enable operation of a slow-shutter mode of an image sensor associated with said associated one image capture device, and the write control signal is a don'"'"'t-write signal when slow-shutter imaging is enabled in said associated one image capture device and the image sensor has not accumulated an image for a predefined slow-shutter speed.

15. The system recited in claim 14 wherein the circuit further comprises:

an enable-detector circuit to detect the enable-slow-shutter signal; and

a generate-don'"'"'t-write-signal circuit to generate the don'"'"'t-write signal.

16. The system recited in claim 15 wherein the circuit further comprises:

a generate-enable signal circuit to generate the enable-slow-shutter signal; and

a detect-don'"'"'t-write-signal circuit to detect the don'"'"'t-write signal, wherein the separate memory maintains a stored image frame in the separate memory when the detect-don'"'"'t-write-signal circuit detects the don'"'"'t-write signal.

17. The system recited in claim 9 wherein the write control signal is separate from said one video signal.

18. The system recited in claim 9 wherein the write control signal is superimposed on said one video signal.

19. The system recited in claim 9 wherein a control signal within said bidirectional signaling is implemented through a unique voltage level superimposed on said one video signal.

20. The system recited in claim 9 wherein a control signal within said bidirectional signaling is a pulse occurring during a vertical blanking interval of said one video signal.

21. The system recited in claim 20 wherein said pulse has one or more predefined pulse widths that specify respective operating modes of said one image capture device.

22. A closed circuit video system that utilizes a shared image store, said system having:

a plurality, N, of image capture devices, each producing a corresponding video signal so as to define a plurality of N video signals;

a circuit, responsive to said plurality of video signals, which in response to a selection control signal, routes a specific group, M, of selected ones of said video signals produced by M respective ones of the N image capture devices to associated output devices, where M and N are positive integers; and

wherein said circuit comprises;

a shared image store operative in conjunction with an associated one of said M video signals produced by a corresponding one of the N image capture devices, said image store implementing a multi-functional shared store for said associated one video signal, through which said image store provides video storage functionality to support both a predefined image store operation and a predefined image processing operation by selectively operating in a first or second mode, respectively, such that said shared image store eliminates a need to have a separate frame store memory situated within or proximate to said corresponding one image capture device, said image store operation being different from said image processing operation; and

said image store communicatively interacts with said corresponding one image capture device through which said corresponding one image capture device instructs said shared image store to operate in said first or second mode so as to provide video storage functionality appropriate to either said image storage operation or said image processing operation as then required by current operation of said corresponding one image capture device.

23. The system recited in claim 22 wherein the circuit comprises a frame grabber, an N×

M video recording multiplexer, an N×

M video matrix switch or an N×

M video selector.

24. The system recited in claim 23 wherein said associated one image capture device comprises a video camera or any other device that produces a video source signal.

25. The system recited in claim 23 wherein said communicative interaction between said associated one image capture device and said separate memory occurs through bi-directional signaling there between, and said first and second modes being write and don'"'"'t write, respectively.

26. The system recited in claim 25 wherein said output devices comprise a plurality of video monitors.

27. The system recited in claim 26 wherein said output devices further comprise at least one video recorder.

28. The system recited in claim 25 wherein the circuit synchronizes capture and refresh display of images from said one video signal produced by said associated one of the image capture devices when said associated one image capture device is operating in a slow shutter image processing mode.

29. The system recited in claim 25 wherein the bidirectional signaling comprises a write control signal produced by said associated one image capture device, wherein the write control signal is a don'"'"'t write signal.

30. The system recited in claim 29 wherein the bidirectional signaling further comprises an enable-slow-shutter signal to enable operation of a slow-shutter mode of an image sensor associated with said associated one image capture device, and the write control signal is a don'"'"'t-write signal when slow-shutter imaging is enabled in said associated one image capture device and the image sensor has not accumulated an image for a predefined slow-shutter speed.

31. The system recited in claim 30 wherein the circuit further comprises:

an enable-detector circuit to detect the enable-slow-shutter signal; and

a generate-don'"'"'t-write-signal circuit to generate the don'"'"'t-write signal.

32. The system recited in claim 31 wherein the circuit further comprises:

a generate-enable signal circuit to generate the enable-slow-shutter signal; and

a detect-don'"'"'t-write-signal circuit to detect the don'"'"'t-write signal, wherein the separate memory maintains a stored image frame in the separate memory when the detect-don'"'"'t-write-signal circuit detects the don'"'"'t-write signal.

33. The system recited in claim 29 wherein the write control signal is separate from said one video signal.

34. The system recited in claim 29 wherein the write control signal is superimposed on said one video signal.

35. The system recited in claim 29 wherein a control signal within said bidirectional signaling is implemented through a unique voltage level superimposed on said one video signal.

36. The system recited in claim 29 wherein a control signal within said bidirectional signaling is a pulse occurring during a vertical blanking interval of said one video signal.

37. The system recited in claim 36 wherein said pulse has one or more predefined pulse widths that specify respective operating modes of said one image capture device.