Method for programming a reference cell

• US 7,064,983 B2
• Filed: 06/05/2003
• Issued: 06/20/2006
• Est. Priority Date: 04/05/2001
• Status: Expired due to Term

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Maayan, Eduardo, Lann, Ameet, Eliyahu, Ron
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/454,820
• Publication Number:
  US 20040081010A1
• Time in Patent Office: 1,111 Days
• Field of Search: 365/185.2, 365/185.18, 365/185.19, 365/185.24, 365/185.28, 365/185.22
• US Class Current: 365/185.2
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.

Claims

1. In an integrated circuit memory on a die having an array of memory cells each exhibiting a native threshold voltage value, a method for programming a reference cell comprising the steps of:

a) driving a golden cell on the die with a predetermined external gate voltage value;

b) programming the reference cell a predetermined amount, the reference cell being driven by a standard gate voltage value which is greater than the predetermined external gate voltage value;

c) sensing the program state of the reference cell relative to the golden cell while the golden cell is driven with the predetermined external gate voltage value; and

d) repeating steps b) and c) until the sensing step indicates that the reference cell has been programmed an amount sufficient to pass a first preselected read operation (V_GB).

2. The method as in claim 1, wherein the predetermined external gate voltage value is the difference D between a first external gate voltage value at which the memory cell in the array which has the highest native threshold voltage value (VTNH) just passes the first preselected read operation (V_GB) and a second external gate voltage value at which a golden cell in the die cell just passes the first preselected read operation (V_GB).

3. The method as in claim 2, including the additional step of locating an address for the VTNH memory cell.

4. The method as in claim 3, wherein the VTNH address-locating step includes the steps of iteratively increasing a gate voltage applied to the memory cells and performing the first preselected read operation at each such applied gate voltage until the first external gate voltage is identified, all of the memory cells in the array passing the first preselected read operation when the first external gate voltage is applied to the memory cells.

5. The method as in claim 4, wherein the step of performing the first preselected read operation in connection with the VTNH address-locating step excludes memory cells that have already passed the first preselected read operation at a previously applied gate voltage.

6. The method as in claim 4, wherein the VTNH address-locating step is accomplished in a single pass through the array.

7. The method as in claim 6, wherein the VTNH address-locating step includes the additional step of performing a second pass through a portion of the array while applying to the memory cells in that portion a gate voltage which is less than the first external gate voltage.

8. The method as in claim 7, wherein the portion is delimited at one end by the address of the VTNH memory cell.

9. The method as in claim 2, wherein the sensing step includes providing a differential comparator with signals respectively generated by the reference cell and the golden cell, the gate of the reference cell being driven with a standard gate voltage level at read (“

read VCCR”

) for the first preselected read operation and the golden cell being driven with a gate voltage level equal to

VCCR-D-M,

wherein M is a predetermined margin, the differential comparator outputting a signal indicative of whether the reference cell signal is higher or lower than the golden cell signal.

10. The method as in claim 9, wherein the signal output by the differential comparator indicates that the first preselected read operation has failed if the reference signal is higher than the golden cell signal and wherein the signal output by the differential comparator indicates that the first preselected read operation has passed if the reference signal is lower than the golden cell signal.

11. The method as in claim 2, wherein the passing the first preselected read operation and passing the first preselected read operation (V_GB) step includes the steps of:

a. setting an initial, low voltage level to be applied to the gate of the memory cells;

b. applying a predetermined gate voltage level to the gate of the reference cell;

c. performing a read operation on consecutive memory cells against the reference cell until a fail-to-read-1 condition is detected;

d. storing the address of the memory cell at which the read operation of step (c) stopped;

e. increasing the voltage level applied to the gates of the memory cells; and

f. repeating steps c, d and e until the entire array has been read,

wherein the VTNH memory cell is the memory cell in the array last stored at step (d).

12. The method as in claim 11, wherein the repeating step commences with the memory cell address stored at step (d).

13. The method as in claim 11, wherein the step of performing a read operation makes one complete pass through the array.

14. The method as in claim 11, wherein the step of increasing the voltage level applied to the gates of the memory cells results in the first external gate voltage value, the first external gate voltage value providing an indication as to whether the threshold voltage of the reference cell is outside of a standard distribution of values.

15. The method as in claim 11, wherein the step of increasing the voltage level applied to the gates of the memory cells results in a the first external gate voltage value, the first external gate voltage value providing an indication as to whether the threshold voltage of one or more of the array cells is outside of a standard distribution of values.

16. The method as in claim 11, wherein the passing the first preselected read operation and passing the first preselected read operation (V_GB) step provides a blank test for the memory array.

17. The method as in claim 11, including the additional step, for at least the VTNH memory cell, of storing the voltage level applied to a low voltage level (“

EXT_VCCR”

) of the gate of the memory cell.