Method and apparatus to reduce latency in a data network wireless radio receiver
First Claim
1. A radio receiver for implementing the physical layer receiving function (PHY) of a wireless data network, the receiver including:
- a receiver front-end for receiving radio signals and including one or more analog-to-digital converters, the receiver front-end providing samples of a received packet of data;
a receive processing pipeline coupled to the receiver front-end to process the provided samples of the received packet of data, the samples entering the receive processing pipeline at a first sample rate;
a counter counting a running count indicative of the number of samples that have entered the processing pipeline;
a comparison unit coupled to the counter for determining from the running count if all the samples of the received packet have entered the pipeline, having an output indicative of whether or not all samples have entered the pipeline; and
a clock unit coupled to the comparison unit output and providing a clock signal to the pipeline, the clock unit causing the processing pipeline to process the samples entering the pipeline at a first rate compatible with the first sample rate until the comparison unit output indicates that all samples have entered the pipeline, thereafter the clock unit causing the processing pipeline to process the samples in the pipeline at a second rate higher than the first rate until the last sample of the packet has been output by the pipeline, such that the processing latency for processing the complete packet is reduced from the case of the processing pipeline processing the samples all at the first rate.
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Accused Products
Abstract
A radio receiver for implementing the physical layer receiving function (PHY) of a wireless data network includes a receive processing pipeline for processing samples of a received packet of data. The samples enter the receive processing pipeline at a first sample rate. A counter generates a running count indicative of the number of samples that have entered the processing pipeline. A comparison unit coupled to the counter determines from the running count if all the samples of the received packet have entered the pipeline. An output of the comparison unit indicates whether or not all samples have entered the pipeline. A clock unit coupled to the comparison unit output provides a clock signal to the pipeline, causing the processing pipeline to process the samples entering the pipeline at a first rate compatible with the first sample rate until the comparison unit output indicates that all samples have entered the pipeline. Thereafter the clock unit causes the processing pipeline to process the samples in the pipeline at a second rate higher than the first rate until the last sample of the packet has been output by the pipeline. The processing latency for processing the complete packet is thus reduced from the case of the processing pipeline processing the samples all at the first data rate.
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Citations
29 Claims
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1. A radio receiver for implementing the physical layer receiving function (PHY) of a wireless data network, the receiver including:
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a receiver front-end for receiving radio signals and including one or more analog-to-digital converters, the receiver front-end providing samples of a received packet of data; a receive processing pipeline coupled to the receiver front-end to process the provided samples of the received packet of data, the samples entering the receive processing pipeline at a first sample rate; a counter counting a running count indicative of the number of samples that have entered the processing pipeline; a comparison unit coupled to the counter for determining from the running count if all the samples of the received packet have entered the pipeline, having an output indicative of whether or not all samples have entered the pipeline; and a clock unit coupled to the comparison unit output and providing a clock signal to the pipeline, the clock unit causing the processing pipeline to process the samples entering the pipeline at a first rate compatible with the first sample rate until the comparison unit output indicates that all samples have entered the pipeline, thereafter the clock unit causing the processing pipeline to process the samples in the pipeline at a second rate higher than the first rate until the last sample of the packet has been output by the pipeline, such that the processing latency for processing the complete packet is reduced from the case of the processing pipeline processing the samples all at the first rate. - View Dependent Claims (2, 3, 4, 5)
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6. A radio receiver comprising:
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a receive processing pipeline for processing samples of a received packet of data, the samples entering the receive processing pipeline at a first sample rate, the pipeline including; a FIFO buffer in the pipeline to receive the samples at the first sample rate; and a transformer in the pipeline with an input coupled to the output of the buffer for performing time-to-frequency conversion on a block of input samples to produce converted samples, the transformer including an input buffer of length at least the number of samples in the block, the transformer further producing an indication of when the transformer input buffer is full with a block of input samples for time-to-frequency conversion, wherein the samples are read out of the FIFO at a second rate higher than the first sample rate until the indication signals that the transformer input buffer is full with a block of samples or until the FIFO is empty in the case that the FIFO is empty before the input buffer contains the block of samples.
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7. A radio receiver comprising:
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a receive processing pipeline for processing samples of a received packet of data, the samples entering the receive processing pipeline at a first sample rate; and a clock generator to generate the clock signal for the receive processing pipeline to process samples at a first processing rate compatible with the first sample rate, the pipeline including; a end of packet detector coupled to the clock generator to determine when and to output an indication of when all the samples of the packet of data have been input into the receive pipeline; wherein the clock generator accepts the indication and in response the indication generates the clock signal for the receive processing pipeline to process samples at a second processing rate higher than the first processing rate until the last sample of the packet has been output by the pipeline. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for processing a packet of data samples received at a radio receiver, comprising the steps of:
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accepting samples from the receiver for processing; counting an indication of the number of samples accepted; processing the accepted samples at a first rate; determining the indication of length of the packet; determining when all the samples of the packet have been accepted; and after all the samples of the packet have been accepted, processing any remaining samples at a second rate higher than the first rate. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. An apparatus for processing a packet of data samples received at a radio receiver, comprising the steps of:
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means for accepting samples from the receiver for processing; means for counting an indication of the number of samples accepted; means for processing the accepted samples; means for determining an indication of length of the packet; means for determining when all the samples of the packet have been accepted; and wherein the means for processing the accepted samples processes the accepted samples at a first rate until all the samples of the packet have been accepted, and thereafter, processing any remaining samples at a second rate higher than the first rate. - View Dependent Claims (24, 25, 26, 27, 28, 29)
wherein determining the packet length indication includes decoding the one or more header frames. -
28. An apparatus as recited in claim 27, wherein the means for counting counts the number of frames processed, and wherein the means for determining when all the samples of the packet have been accepted includes comparing the count to the determined packet length indication.
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29. An apparatus as recited in claim 27, wherein the means for counting counts the number of samples processed, and wherein the means for determining when all the samples of the packet have been accepted includes comparing the count to the determined packet length indication.
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Specification