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Redundant telecommunication system using memory equalization apparatus and method of operation

  • US 7,065,098 B2
  • Filed: 04/20/2001
  • Issued: 06/20/2006
  • Est. Priority Date: 01/19/2001
  • Status: Active Grant
First Claim
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1. For use in a redundant, high-availability system of processor-based components, a system for memory equalization comprising:

  • a memory containing data elements each stored within one of a plurality of defined memory segments, wherein the data elements within the memory segments may be selectively changed;

    a direct memory access circuit automatically copying memory segments from the memory to a queue without utilizing a processor changing the memory segments;

    a data link coupled to the queue, wherein each of the plurality of memory segments is structured to form a data packet which may be transmitted without internal changes over the data link; and

    a control preventing the memory segments from receiving changes to the data elements contained therein faster than transfer of data elements within the memory segments over the data link.

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