Redundant telecommunication system using memory equalization apparatus and method of operation

• US 7,065,098 B2
• Filed: 04/20/2001
• Issued: 06/20/2006
• Est. Priority Date: 01/19/2001
• Status: Active Grant

• Current Assignee: Access Solutions, Ltd. (LOXAM SAS)
• Original Assignee: Raze Technologies, Inc.
• Inventors: Struhsaker, Paul F., Kulkarni, Sanjay D., Denton, James S.
• Primary Examiner(s): Pezzlo, John
• Application Number:
  US09/839,259
• Publication Number:
  US 20020097670A1
• Time in Patent Office: 1,887 Days
• Field of Search: 370/347, 370/278, 370/233, 370/332, 370/352, 370/395.1, 370/230, 370/412, 370/417, 370/428, 370/429, 370/395.71, 375/233, 375/332, 709/205, 709/238, 710/113, 455/11.1, 711/167
• US Class Current: 370/429
• CPC Class Codes: H01Q 1/246 specially adapted for base stations
• CPC Class Codes: H04L 1/0005 applied to payload information
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0017 where the mode-switching is based on Quality of Service requirement
• CPC Class Codes: H04L 1/007 Unequal error protection for format H04L1/0078; for codes per se H03M13/35
• CPC Class Codes: H04L 12/10 Current supply arrangements
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: H04L 2001/0098 Unequal error protection
• CPC Class Codes: H04M 2207/206 composed of PSTN and wireless network
• CPC Class Codes: H04M 2242/04 for emergency applications
• CPC Class Codes: H04M 2242/06 Lines and connections with preferential service
• CPC Class Codes: H04M 3/42 Systems providing special services or facilities to subscribers specially adapted for wireless communication networks H04W4/00
• CPC Class Codes: H04W 28/18 Negotiating wireless communication parameters
• CPC Class Codes: H04W 84/14 WLL [Wireless Local Loop]; RLL [Radio Local Loop]
• CPC Class Codes: H04W 88/021 adapted for Wireless Local Loop operation
• CPC Class Codes: H04W 88/08 Access point devices

Abstract

Data which must be memory equalized across a redundant, high availability system utilizing processor-based components is structured in memory segments which form data packets for a data link between active and standby components. Direct memory access is employed to copy memory segments within the active component into a queue for the data link, which transfers memory segments without utilizing the processor within the active component while automatically verifying data integrity and acknowledging successful data transfers. The direct memory access copying of memory segments to the queue may be triggered for changed memory segments by either the processor or specialized hardware within the active component, or may be run in a continuous loop sequencing through a predefined range of memory segments. The standby component may thus be kept abreast of changes to data within memory segments, such as changes to call states or resource allocation records relating to call processing.

Claims

1. For use in a redundant, high-availability system of processor-based components, a system for memory equalization comprising:

a memory containing data elements each stored within one of a plurality of defined memory segments, wherein the data elements within the memory segments may be selectively changed;

a direct memory access circuit automatically copying memory segments from the memory to a queue without utilizing a processor changing the memory segments;

a data link coupled to the queue, wherein each of the plurality of memory segments is structured to form a data packet which may be transmitted without internal changes over the data link; and

a control preventing the memory segments from receiving changes to the data elements contained therein faster than transfer of data elements within the memory segments over the data link.

2. The system as set forth in claim 1, further comprising:

a processor intermittently changing data elements within the memory segments, wherein the data link operates without direct control by the processor.

3. The system as set forth in claim 1, wherein the memory further comprises a set of memory segments mapping to a corresponding set of memory segments within a device coupled to the data link.

4. The system as set forth in claim 1, wherein the memory further comprises a portion of Firewire Global Memory and wherein the data link comprises a Firewire data link.

5. The system as set forth in claim 1, wherein each of the data elements further comprise one of the following:

call state information for a call being processed;

resource allocation records for resources allocated to a call being processed; and

other information regarding a call being processed.

6. The system as set forth in claim 1, wherein the direct memory access circuit copies memory segments containing changed data elements therein from the memory to the queue, the copying of a memory segment being triggered by a processor which intermittently changes data elements within the memory segments.

7. The system as set forth in claim 6, wherein the processor writes a direct memory access descriptor for a memory segment containing a changed data element and sets controls bits initiating copying of the memory segment by the direct memory access circuit.

8. The system as set forth in claim 1, wherein the direct memory access circuit copies memory segments containing changed data elements therein from the memory to the queue, the copying of a memory segment being triggered by a circuit monitoring writes to preselected memory addresses to detect changes to a data element within any memory segment.

9. The system as set forth in claim 1, wherein the direct memory access circuit sequentially copies each of the memory segments from the memory to the queue in a continuous loop.

10. The system as set forth in claim 1, wherein the data link operates in accordance with an asynchronous transfer mode.

11. A redundant, high-availability system of processor-based components, comprising:

an active component;

a standby component; and

a system for memory equalization between the active and standby components comprising;

counterpart memories within the active and standby components each containing data elements stored within one of a plurality of defined memory segments mapped to addresses within both of the counterpart memories, wherein the data elements within the memory segments may be selectively changed;

a direct memory access circuit within each of the active and standby components, the direct memory access circuit within the active component capable of automatically copying memory segments from the memory within the active component to a queue within the active component without utilizing a processor within the active component changing the memory segments within the active component and the direct memory access circuit within the standby component capable of automatically copying memory segments from a queue within the standby component to the memory within the standby component without utilizing a processor within the standby component changing the memory segments within the standby component;

a data link coupling to the queue within the active component to the queue within the standby component, wherein each of the plurality of memory segments is structured to form a data packet which may be transmitted without internal changes over the data link; and

a control within the active component preventing the memory segments within the memory in the active component from receiving changes to the data elements contained therein faster than transfer of data elements within the memory segments over the data link.

12. The system as set forth in claim 11, wherein the active component further comprises:

a processor intermittently changing data elements within the memory segments, wherein the data link operates without direct control by the processor.

13. The system as set forth in claim 11, wherein the counterpart memories within the active and standby components each further comprise a set of memory segments mapping to a common set of addresses.

14. The system as set forth in claim 11, wherein the counterpart memories within the active and standby components further comprise a portion of Firewire Global Memory and wherein the data link comprises a Firewire data link.

15. The system as set forth in claim 11, wherein each of the data elements within either of the counterpart memories further comprise one of the following:

call state information for a call being processed;

resource allocation records for resources allocated to a call being processed; and

other information regarding a call being processed.

16. The system as set forth in claim 11, wherein the direct memory access circuit within the active component copies memory segments containing changed data elements therein from the memory within the active component to the queue within the active component, the copying of a memory segment being triggered by a processor within the active component which intermittently changes data elements within the memory segments within the active component.

17. The system as set forth in claim 16, wherein the processor within the active component writes a direct memory access descriptor for a memory segment within the active component which contains a changed data element and sets controls bits initiating copying of the memory segment within the active component by the direct memory access circuit within the active component.

18. The system as set forth in claim 11, wherein the direct memory access circuit within the active component copies memory segments containing changed data elements therein from the memory within the active component to the queue within the active component, the copying of a memory segment being triggered by a circuit within the active component which monitor writes to preselected memory addresses to detect changes to a data element within any memory segment within the active component.

19. The system as set forth in claim 11, wherein the direct memory access circuit within the active component sequentially copies each of the memory segments from the memory within the active component to the queue within the active component in a continuous loop.

20. The system as set forth in claim 11, wherein a controller for the data link within the standby component verifies data integrity for data packets received over the data link and acknowledges successful transfer of data packets over the data link to the active component.

21. The system as set forth in claim 11, wherein the direct memory access circuit within the standby component automatically moves memory segments from a queue within the standby component coupled to the data link into a corresponding memory location in the memory within the standby component.

22. The system as set forth in claim 11, wherein the data link operates in accordance with an asynchronous transfer mode.

23. The system as set forth in claim 11, wherein the active component is one of N active components supported by the standby component.

24. For use in a redundant, high-availability system of processor-based components, a method of memory equalization comprising the steps of:

selectively changing data elements each stored within one of a plurality of defined memory segments contained within a memory;

automatically copying memory segments from the memory to a queue utilizing a direct memory access circuit and without utilizing a processor changing the memory segments;

transferring memory segments over a data link coupled to the queue, wherein each of the plurality of memory segments is structured to form a data packet which may be transmitted without internal changes over the data link; and

inhibiting the memory segments from receiving changes to the data elements contained therein faster than transfer of data elements within the memory segments over the data link.

25. The method as set forth in claim 24, further comprising:

intermittently changing data elements within the memory segments utilizing a processor, wherein the data link operates without direct control by the processor.

26. The method as set forth in claim 24, further comprising:

mapping the memory segments to a common set of addresses for counterpart memory segments within a standby component.

27. The method as set forth in claim 26, wherein the steps of mapping the memory segments to a common set of addresses for counterpart memory segments within a standby component and transferring memory segments over a data link coupled to the queue further comprise:

mapping a portion of Firewire Global Memory to the memory segments and the counterpart memory segments; and

transferring memory segments over a Firewire data link.

28. The method as set forth in claim 24, further comprising:

storing one of the following within each of the data elements;

call state information for a call being processed;

resource allocation records for resources allocated to a call being processed; and

other information regarding a call being processed.

29. The method as set forth in claim 24, wherein the step of automatically copying memory segments from the memory to a queue utilizing a direct memory access circuit further comprises:

initiating copying of a memory segment by a processor within an active component containing the memory segment, wherein the processor intermittently changes data elements within the memory segments within the active component.

30. The method as set forth in claim 29, further comprising:

writing a direct memory access descriptor for a memory segment within the active component which contains a changed data element; and

setting controls bits initiating copying of the memory segment which contains the changed data element by the direct memory access circuit.

31. The method as set forth in claim 24, wherein the step of automatically copying memory segments from the memory to a queue utilizing a direct memory access circuit further comprises:

initiating copying of a memory segment by a circuit within an active component containing the memory segment, wherein the circuit monitor writes to preselected memory addresses to detect changes to a data element within any memory segment within the active component.

32. The method as set forth in claim 24, wherein the step of automatically copying memory segments from the memory to a queue utilizing a direct memory access circuit further comprises:

utilizing the direct memory access circuit, sequentially copying each memory segment from the memory to the queue in a continuous loop.

33. The method as set forth in claim 24, wherein the step of transferring memory segments over a data link coupled to the queue further comprises:

transmitting the memory segments to a standby component coupled to the data link, wherein a controller for the data link within the standby component verifies data integrity for data packets received over the data link and acknowledges successful transfer of data packets over the data link to an active component containing the queue.

34. The method as set forth in claim 33, wherein the step of transmitting the memory segments to a standby component coupled to the data link further comprises:

receiving the memory segments in a queue within the standby component, wherein a direct memory access circuit within the standby component automatically moves memory segments from the queue within the standby component into a corresponding memory location in a memory within the standby component.

35. The method as set forth in claim 24, wherein the step of transferring memory segments over a data link coupled to the queue further comprises:

transmitting the memory segments utilizing an asynchronous transfer mode switch.

36. The method as set forth in claim 24, further comprising:

supporting processing within an active component containing the memory and the queue utilizing a standby component coupled to the data link, wherein the active component is one of N active components supported by the standby component.