Remote control receiving system

• US 7,065,332 B2
• Filed: 08/08/2003
• Issued: 06/20/2006
• Est. Priority Date: 08/09/2002
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Tomida, Yasuyuki, Kitamura, Koji, Mori, Hironobu
• Primary Examiner(s): Le, Lana
• Application Number:
  US10/636,652
• Publication Number:
  US 20040059531A1
• Time in Patent Office: 1,047 Days
• Field of Search: 455/352, 455/151.1, 455/92, 455/152.1, 455/151.2, 340/825.69, 340/825.72, 340/5.72, 340/5.63, 702/79, 702/63
• US Class Current: 455/151.2
• CPC Class Codes: G08C 17/00 Arrangements for transmitting signals characterised by the use of a wireless electrical link

Abstract

A remote control receiving circuit for receiving a remote control signal from a transmitter includes a header interrupt generation circuit that outputs a header interrupt signal when detecting the header of the signal, a data interrupt generation circuit that outputs a data interrupt signal when the header has been detected and the predetermined data receiving is completed, and a switch that selects the header interrupt signal or data interrupt signal in accordance with an instruction of the CPU. A CPU has one interrupt port for receiving the interrupt signal selected by the switch, and performs control in accordance with the received interrupt signal. Therefore, a remote control receiving system can reduce the codes, processing power, and resources of the CPU, which are used to implement the remote control signal receiving function, and reduce the cost of the entire system.

Claims

1. A remote control receiving system that is constituted by a remote control receiving circuit for receiving a remote control signal having a header part, and a data part corresponding to a remote control button depressed;

and a CPU for controlling the remote control receiving circuit to decode the remote control signal received by the remote control receiving circuit,

said remote control receiving circuit comprising;

an edge detection circuit that detects rising edges and falling edges of the remote control signal;

a counter circuit that counts a time interval between a rising edge and a falling edge of the remote control signal, and a time interval between a falling edge and a rising edge;

a header detection circuit that detects the header part of the remote control signal on the basis of the count value of the counter circuit;

a data determination circuit that determines 0 or 1 of the data part in the remote control signal on the basis of the count value of the counter circuit, and stores the determination result in an internal register;

a header interrupt generation circuit that outputs a header interrupt signal notifying detection of the header part in the remote control signal to the CPU, when the header part of the remote control signal is detected by the header detection circuit;

a data interrupt generation circuit that outputs a data interrupt signal notifying a data receiving completion for the remote control signal to the CPU, when data corresponding to the number of bits, which number has been previously specified by the CPU, are stored in the internal register by the data determination circuit after the header part of the remote control signal is detected by the header detection circuit; and

a switch that selects one of the header interrupt signal and the data interrupt signal in accordance with an instruction of the CPU,

said CPU having one interrupt port, and receiving the interrupt signal through the switch of the remote control receiving circuit, thereby controlling the remote control receiving circuit in accordance with the received interrupt signal, and determining that the remote control button is released when the interrupt signal from the switch is not received during a predetermined time period.

2. The remote control receiving system of claim 1 wherein

the CPU instructs the switch to select the data interrupt signal at start of the operation of the remote control receiving system or at detection of release of the remote control button.

3. The remote control receiving system of claim 1 wherein

when the remote control receiving circuit receives the remote control signal that has the header part and the data part, and successively receives a remote control signal that is composed only of a repeat header part without including the data part,

the CPU instructs the switch to select the data interrupt signal at start of the operation of the remote control receiving system, then instructs to select the header interrupt after receiving the data interrupt signal from the remote control receiving circuit through the interrupt port, and instructs to select the data interrupt signal again when release of the remote control button is detected.

4. The remote control receiving system of claim 1 wherein

after the data corresponding to the number of bits, which number has been previously specified by the CPU, are stored in the internal register, the data determination circuit does not update the data that are stored in the internal register until the header detection circuit detects the next header part.

5. The remote control receiving system of claim 1 wherein

when receiving the next header part before the data corresponding to the number of bits, which has been previously specified by the CPU are stored in the internal register, the data determination circuit gives a higher priority to detection of the next header part in the header detection circuit.

6. The remote control receiving system of claim 1 wherein

when the data part of the remote control signal is composed of a main data part, and an inverted data part that is obtained by inverting 0 and 1 of the main data part,

the remote control receiving circuit includes a validity determination circuit that compares the main data part and the inverted data part of data stored in the internal register with each other, and determines the data to be valid when all of corresponding bits have different values while determining the data to be invalid in other cases, and

the data interrupt generation circuit outputs the data interrupt signal when the data corresponding to the number of bits, which has been previously specified by the CPU, are stored in the internal register by the data determination circuit, and the data stored in the internal register are determined to valid by the validity determination circuit, after the header part of the remote control signal is detected by the header detection circuit.

7. The remote control receiving system of claim 6 wherein

the remote control receiving circuit includes:

an OFF counter that continues to count up until a time period that has been previously specified by the CPU expires, and is reset when one of two conditions, which is specified by the CPU, that the header part of the remote control signal is detected by the header detection circuit, or that data corresponding to the number of bits, which has been previously specified by the CPU, are stored in the internal register by the data determination circuit and the data stored in the internal register are determined to be valid by the validity determination circuit, is met; and

an OFF detection circuit that makes an ON flag rise when the OFF counter is reset, and makes the ON flag fall when the count value of the OFF counter and the period that has been previously specified by the CPU become equal to each other, and

the CPU judges that the remote control button is released when the ON flag falls.

8. The remote control receiving system of claim 1 wherein

the remote control receiving circuit includes an OFF detection circuit that makes an OFF flag rise when detecting that a logic level specified by the CPU continues for a longer time period than a period that has been previously specified by the CPU, on the basis of the count result by the counter circuit, and

the CPU judges that the remote control button is released when the OFF flag rises.

9. The remote control receiving system of claim 1 wherein

in a case where the header part of the remote control signal is composed of a waveform that keeps a certain logic level for a prescribed time period, and a waveform that keeps an opposite logic level for a prescribed time period,

when the counter circuit detects a change in the logic level during a time period that has been previously specified by the CPU while the remote control receiving circuit is receiving a header part of the remote control signal, the counter circuit ignores the change in the logic level during the time period as a noise and starts counting from a count value before the logic level changes.

10. A remote control receiving system that is constituted by a remote control receiving circuit for receiving a remote control signal having a header part, and a data part corresponding to a remote control button depressed;

and a CPU for controlling the remote control receiving circuit to decode the remote control signal received by the remote control receiving circuit, wherein

when the data part of the remote control signal is composed of a main data part, and an inverted data part that is obtained by inverting 0 and 1 of the main data part,

said remote control receiving circuit comprises;

an edge detection circuit that detects rising edges and falling edges of the remote control signal;

a counter circuit that counts a time interval between a rising edge and a falling edge of the remote control signal, and a time interval between a falling edge and a rising edge;

a header detection circuit that detects the header part of the remote control signal on the basis of the count value of the counter circuit;

a data determination circuit that determines 0 or 1 of the data part in the remote control signal on the basis of the count value of the counter circuit, and stores the determination result in an internal register;

a validity determination circuit that compares the main data part and the inverted data part of the data stored in the internal register with each other, and determines the data to be valid when all of corresponding bits have different values while determining the data to be invalid in other cases;

an OFF counter that continues to count up until a time period that has been previously specified by the CPU expires, and is reset when one of two conditions, which is specified by the CPU, that the header part of the remote control is detected by the header detection circuit, or that data corresponding to the number of bits, which has been previously specified by the CPU, are stored in the internal register by the data determination circuit and the data stored in the internal register are determined to be valid by the validity determination circuit, is met,

an OFF detection circuit that makes an ON flag rise when the OFF counter is reset, and makes the ON flag fall when the time period that has been previously specified by the CPU and the count value of the OFF counter become equal to each other; and

a data header flag that is set when the OFF counter is reset, and is reset by the CPU, and

said CPU reads the value of the data header flag and the value of the ON flag in prescribed timings, respectively, and controls the remote control receiving circuit in accordance with the read values.