Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer
First Claim
1. A method for debugging an electronic system having instrumentation circuitry included therein, the electronic system being coupled to at least one logic analyzer, wherein the electronic system is described with a HDL, said method comprising:
- (a) activating certain design visibility, design patching or design control aspects of the instrumentation circuitry available for examining or modifying the electronic system via the instrumentation circuitry;
(b) determining configuration information based on the certain design visibility, design patching or design control aspects that are activated;
(c) configuring the instrumentation circuitry in accordance with the configuration information;
(d) configuring the instrumentation circuitry to interoperate with the at least one logic analyzer;
(e) receiving debug data from the configured instrumentation circuitry operating within the electronic system product;
(f) translating the debug data into HDL-related debug information; and
(g) relating the HDL-related debug information to the HDL description.
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Accused Products
Abstract
Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
221 Citations
27 Claims
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1. A method for debugging an electronic system having instrumentation circuitry included therein, the electronic system being coupled to at least one logic analyzer, wherein the electronic system is described with a HDL, said method comprising:
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(a) activating certain design visibility, design patching or design control aspects of the instrumentation circuitry available for examining or modifying the electronic system via the instrumentation circuitry; (b) determining configuration information based on the certain design visibility, design patching or design control aspects that are activated; (c) configuring the instrumentation circuitry in accordance with the configuration information; (d) configuring the instrumentation circuitry to interoperate with the at least one logic analyzer; (e) receiving debug data from the configured instrumentation circuitry operating within the electronic system product; (f) translating the debug data into HDL-related debug information; and (g) relating the HDL-related debug information to the HDL description. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A computer readable storage medium including at least computer program code for debugging an electronic system having instrumentation circuitry included therein, the electronic system being coupled to at least one logic analyzer, wherein the electronic system is described with a HDL, said computer readable medium comprising:
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computer program code for activating certain design visibility, design patching or design control aspects of the instrumentation circuitry available for examining or modifying the electronic system via the instrumentation circuitry; computer program code for determining configuration information based on the certain design visibility, design patching or design control aspects that are activated; computer program code for configuring the instrumentation circuitry in accordance with the configuration information; computer program code for configuring the instrumentation circuitry to interoperate with the at least one logic analyzer; computer program code for receiving debug data from the configured instrumentation circuitry operating within the electronic system product; computer program code for translating the debug data into HDL-related debug information; and computer program code for relating the HDL-related debug information to the HDL description. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification