Address translation logic for use in a GPS receiver
First Claim
1. A GPS receiver comprising:
- address translation logic adapted to provide a plurality of translated addresses each based on an address from memory access logic;
said memory access logic adapted to provide each said address to said address translation logic;
memory adapted to store data in a plurality of memory locations corresponding to said plurality of translated addresses; and
circuitry adapted to provide said data to said memory based on a signal received by the GPS receiver, wherein said data comprises a plurality of subsets each having a plurality of data elements;
wherein said address translation logic provides said plurality of translated addresses based on organizing said data such that each of said plurality of data elements associated with each of said plurality of subsets are grouped together in said memory, each of said plurality of subsets corresponds to results of a correlation of said signal with a generated frequency and a generated code at a one of a plurality of time offsets, and each of said plurality of data elements in each of said plurality of subsets corresponds to a partial correlation sample from a time limited accumulation of data from the results of the correlation of said signal with said generated frequency and said generated code at said one of said plurality of time offsets.
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Abstract
The address translation logic of the present invention is incorporated in a global positioning system (GPS) receiver and operates to group data in memory based on translating the address from a direct memory access controller. The data includes post-correlated samples of the correlation of a signal with a generated frequency and a generated code having a plurality of time offsets. In general, the address translation logic organizes the data such that each element of the data associated with particular ones of the plurality of time offsets are grouped together in order to improve the efficiency of performing a fast Fourier transform of the data. In addition, the address translation logic allows the transfer of data from correlation circuitry to memory, from the memory to an FFT module, and from the FFT module to the memory using standard DMA controllers.
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Citations
20 Claims
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1. A GPS receiver comprising:
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address translation logic adapted to provide a plurality of translated addresses each based on an address from memory access logic; said memory access logic adapted to provide each said address to said address translation logic; memory adapted to store data in a plurality of memory locations corresponding to said plurality of translated addresses; and circuitry adapted to provide said data to said memory based on a signal received by the GPS receiver, wherein said data comprises a plurality of subsets each having a plurality of data elements; wherein said address translation logic provides said plurality of translated addresses based on organizing said data such that each of said plurality of data elements associated with each of said plurality of subsets are grouped together in said memory, each of said plurality of subsets corresponds to results of a correlation of said signal with a generated frequency and a generated code at a one of a plurality of time offsets, and each of said plurality of data elements in each of said plurality of subsets corresponds to a partial correlation sample from a time limited accumulation of data from the results of the correlation of said signal with said generated frequency and said generated code at said one of said plurality of time offsets.
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2. A GPS receiver comprising:
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circuitry adapted to provide a serial data stream comprising a plurality of subsets each comprising a plurality of data elements based on a signal received by the GPS receiver; memory adapted to receive said serial data stream and store said plurality of data elements for each of said plurality of subsets based on a plurality of translated addresses; memory access logic adapted to provide a plurality of sequential addresses; and address translation logic adapted to translate said plurality of sequential addresses into said plurality of translated addresses such that, for each of said plurality of subsets, said plurality of data elements for said subset are grouped together in said memory. - View Dependent Claims (3, 4, 5, 6, 7, 8)
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9. A GPS receiver comprising:
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circuitry adapted to provide a serial data stream comprising a plurality of subsets each comprising a plurality of data elements based on a baseband signal; memory adapted to receive said serial data stream and store said plurality of data elements for each of said plurality of subsets based on a plurality of translated addresses; memory access logic adapted to provide a plurality of sequential addresses; address translation logic adapted to translate said plurality of sequential addresses into said plurality of translated addresses such that, for each of said plurality of subsets, said plurality of data elements for said subset are grouped together in said memory; and a receiver frontend adapted to receive a GPS signal and process the GPS signal to provide said baseband signal. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A GPS receiver comprising:
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means for providing a serial data stream comprising a plurality of subsets each comprising a plurality of data elements based on a signal received by the GPS receiver; means for storing said plurality of data elements for each of said plurality of subsets based on a plurality of translated addresses; means for providing a plurality of sequential addresses; and means for translating said plurality of sequential addresses into said plurality of translated addresses such that, for each of said plurality of subsets, said plurality of data elements for said subset are grouped together in said means for storing. - View Dependent Claims (17, 18, 19, 20)
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Specification