Metric calculation design for variable code rate decoding of broadband trellis, TCM, or TTCM

• US 7,065,695 B2
• Filed: 10/04/2002
• Issued: 06/20/2006
• Est. Priority Date: 05/31/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Tran, Hau Thien, Cameron, Kelly Brian, Lau, Linda K.
• Primary Examiner(s): Lamarre, Guy J.
• Application Number:
  US10/264,647
• Publication Number:
  US 20030226087A1
• Time in Patent Office: 1,355 Days
• Field of Search: 714/755, 714/701, 714/786, 714/792, 714794-796, 714/759, 375/262, 375/265, 375/261, 375/341, 375/279
• US Class Current: 714/755
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/2767 Interleaver wherein the permutation pattern or a portion thereof is stored
• CPC Class Codes: H03M 13/2771 Internal interleaver for turbo codes H03M13/2714 and H03M13/2725 take precedence
• CPC Class Codes: H03M 13/2785 Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/4123 implementing the return to a predetermined state
• CPC Class Codes: H03M 13/4161 implementing path management
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/0066 Parallel concatenated codes
• CPC Class Codes: H04L 1/0068 by puncturing
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

Metric calculation design for variable code rate decoding of broadband trellis, TCM (trellis coded modulated), or TTCM (turbo trellis coded modulation). A single design can accommodate a large number of code rates by multiplexing the appropriate paths within the design. By controlling where to scale for any noise of a received symbol within a received signal, this adaptable design may be implemented in a manner that is very efficient in terms of performance, processing requirements (such as multipliers and gates), as well as real estate consumption. In supporting multiple code rates, appropriately selection of the coefficients of the various constellations employed, using the inherent redundancy and symmetry along the I and Q axes, can result in great savings of gates borrowing upon the inherent redundancy contained therein; in addition, no subtraction (but only summing) need be performed when capitalizing on this symmetry.

Claims

1. A metric generator that determines a metric associated with a received symbol according to a rate control sequence, the metric generator comprising:

a plurality of predetermined in-phase (I) coefficients;

a plurality of predetermined quadrature (Q) coefficients;

a plurality of I summing blocks that selectively sums an I component of the received symbol with each of the predetermined I coefficients thereby generating a plurality of I sums;

a plurality of Q summing blocks that selectively sums a Q component of the received symbol with each of the predetermined Q coefficients thereby generating a plurality of Q sums;

a plurality of I squaring blocks that squares each I sum of the plurality of I sums thereby generating a plurality of squared I sums;

a plurality of Q squaring blocks that squares each Q sum of the plurality of Q sums thereby generating a plurality of squared Q sums;

a square output multiplexor that receives the plurality of squared I sums and the plurality of squared Q sums and outputs a plurality of I outputs and a plurality of Q outputs;

a plurality of I,Q summing blocks that selectively sums the plurality of I outputs and the plurality of Q outputs from the square output multiplexor according to the rate control sequence thereby generating a plurality of I,Q outputs;

a plurality of min* processing blocks that processes the plurality of I,Q outputs according to the rate control sequence thereby generating a plurality of output metrics; and

a metric output multiplexor that selects an output metric from the plurality of output metrics according to the rate control sequence.

2. The metric generator of claim 1, wherein the rate control sequence comprises a plurality of modulations;

and each modulation of the plurality of modulations comprises a constellation and a mapping.

3. The metric generator of claim 2, wherein:

the plurality of predetermined I coefficients and the plurality of predetermined Q coefficients comprise symmetry along I and Q axes of the constellation;

the plurality of I summing blocks selectively sums the I component of the received symbol with each of the predetermined I coefficients by employing the symmetry; and

the plurality of Q summing blocks selectively sums the Q component of the received symbol with each of the predetermined Q coefficients by employing the symmetry.

4. The metric generator of claim 2, wherein one modulation of the plurality of modulations comprises at least one of 8 Phase Shift Keying (PSK) modulation, Quadrature Phase Shift Keying (QPSK) modulation, 16 Quadrature Amplitude Modulation (QAM), and 16 Amplitude Phase Shift Keying (APSK) modulation.

5. The metric generator of claim 1, further comprising a plurality of variance scaling blocks that scales the plurality of I,Q outputs based on a signal to noise ratio of the received symbol.

6. The metric generator of claim 1, further comprising a plurality of sigma scaling blocks that scales the plurality of I sums and the plurality of Q sums based on a signal to noise ratio of the received symbol.

7. The metric generator of claim 1, further comprising a plurality of sigma scaling blocks that scales the plurality of predetermined I coefficients and the plurality of predetermined Q coefficients based on a signal to noise ratio of the received symbol.

8. The metric generator of claim 1, further comprising a plurality of sigma scaling blocks that scales the I component of the received symbol and the Q component of the received symbol based on a signal to noise ratio of the received symbol.

9. The metric generator of claim 1, further comprising a plurality of at least one of mm processing blocks, max processing blocks, and max* processing blocks that processes the plurality of I,Q outputs according to the rate control sequence thereby generating a plurality of output metrics.

10. The metric generator of claim 1, wherein the square output multiplexor employs a look up table that comprises a plurality of predetermined square output MUX selections defined according to the rate control sequence.

11. The metric generator of claim 1, wherein the metric output multiplexor employs a look up table that comprises a plurality of predetermined metric output MUX selections defined according to the rate control sequence.

12. The metric generator of claim 1, wherein the metric generator is contained within a turbo trellis coded modulation (TTCM) decoder.

13. The metric generator of claim 12, wherein the TTCM decoder comprises a variable code rate TTCM decoder.

14. The metric generator of claim 1, wherein the metric generator is contained within at least one of a satellite receiver, a high definition television (HDTV) set top box receiver, a mobile receiver, a base station receiver, a receiver, and a transceiver.

15. The metric generator of claim 1, wherein the metric generator is contained within a decoder that decodes information that is received at a rate greater than substantially 80 mega-bits per second.

16. The metric generator of claim 1, wherein the received symbol is encoded using a systematic encoder.

17. The metric generator of claim 1, wherein the received symbol is encoded using a non-systematic encoder.

18. A metric generator that determines a metric associated with a received symbol according to a rate control sequence, the metric generator comprising:

a square output multiplexor that selectively outputs a plurality of in-phase (I) associated outputs and a plurality of quadrature (Q) associated outputs according to the rate control sequence;

wherein the rate control sequence comprises a plurality of modulations;

wherein each modulation of the plurality of modulations comprises a constellation and a mapping;

wherein the plurality of I associated outputs being indicative of I-axis distances separating an I component of the received symbol and a plurality of predetermined I coefficients corresponding to the constellation; and

wherein the plurality of Q associated outputs being indicative of Q-axis distances separating a Q component of the received symbol and a plurality of predetermined Q coefficients corresponding to the constellation; and

a plurality of min* processing blocks that processes selected I,Q sums according to the rate control sequence to generate a plurality of output metrics, wherein the selected I,Q sums comprising sums of an I associated output from the plurality of I associated outputs and a Q associated output from the plurality of Q associated outputs; and

a metric output multiplexor that selects an output metric from the plurality of output metrics according to the rate control sequence.

19. The metric generator of claim 18, further comprising a plurality of variance scaling blocks that scales the selected I,Q sums based on a signal to noise ratio of the received symbol.

20. The metric generator of claim 18, further comprising:

a plurality of predetermined in-phase (I) coefficients;

a plurality of predetermined quadrature (Q) coefficients;

a plurality of I summing blocks that selectively sums an I component of the received symbol with each of the predetermined I coefficients thereby generating a plurality of I sums;

a plurality of Q summing blocks that selectively sums a Q component of the received symbol with each of the predetermined Q coefficients thereby generating a plurality of Q sums;

a plurality of I squaring blocks that squares each I sum of the plurality of I sums thereby generating the plurality of I associated outputs; and

a plurality of Q squaring blocks that squares each Q sum of the plurality of Q sums thereby generating the plurality of Q associated outputs.

21. The metric generator of claim 20, wherein:

the plurality of predetermined I coefficients and the plurality of predetermined Q coefficients comprise symmetry along I and Q axes of the constellation;

the plurality of I summing blocks selectively sums the I component of the received symbol with each of the predetermined I coefficients by employing the symmetry; and

the plurality of Q summing blocks selectively sums the Q component of the received symbol with each of the predetermined Q coefficients by employing the symmetry.

22. The metric generator of claim 20, further comprising a plurality of sigma scaling blocks that scales the plurality of I sums and the plurality of Q sums based on a signal to noise ratio of the received symbol.

23. The metric generator of claim 20, further comprising a plurality of sigma scaling blocks that scales the plurality of predetermined I coefficients and the plurality of predetermined Q coefficients based on a signal to noise ratio of the received symbol.

24. The metric generator of claim 20, further comprising a plurality of sigma scaling blocks that scales the I component of the received symbol and the Q component of the received symbol based on a signal to noise ratio of the received symbol.

25. The metric generator of claim 18, further comprising a plurality of at least one of mm processing blocks, max processing blocks, and max* processing blocks that processes selected I,Q sums according to the rate control sequence to generate the plurality of output metrics.

26. The metric generator of claim 18, wherein the square output multiplexor employs a look up table that comprises a plurality of predetermined square output MUX selections defined according to the rate control sequence.

27. The metric generator of claim 18, wherein the metric output multiplexor employs a look up table that comprises a plurality of predetermined metric output MUX selections defined according to the rate control sequence.

28. The metric generator of claim 18, wherein one modulation of the plurality of modulations comprises at least one of 8 Phase Shift Keying (PSK) modulation, Quadrature Phase Shift Keying (QPSK) modulation, 16 Quadrature Amplitude Modulation (QAM), and 16 Amplitude Phase Shift Keying (APSK) modulation.

29. The metric generator of claim 18, wherein the metric generator is contained within a turbo trellis coded modulation (TTCM) decoder.

30. The metric generator of claim 29, wherein the TTCM decoder comprises a variable code rate TTCM decoder.

31. The metric generator of claim 18, wherein the metric generator is contained within at least one of a satellite receiver, a high definition television (HDTV) set top box receiver, a mobile receiver, a base station receiver, a receiver, and a transceiver.

32. The metric generator of claim 18, wherein the metric generator is contained within a decoder that decodes information that is received at a rate greater than substantially 80 mega-bits per second.

33. The metric generator of claim 18, wherein the received symbol is encoded using a systematic encoder.

34. The metric generator of claim 18, wherein the received symbol is encoded using a non-systematic encoder.

35. A metric generator that determines a metric associated with a received symbol according to a rate control sequence, the metric generator comprising:

a plurality of sigma scaling blocks that scales an in-phase (I) component of the received symbol and a quadrature (Q) component of the received symbol based on a signal to noise ratio of the received symbol;

a plurality of predetermined, scaled I coefficients that are scaled based on the signal to noise ratio of the received symbol; and

a plurality of predetermined, scaled Q coefficients that are scaled based on the signal to noise ratio of the received symbol;

a plurality of I summing blocks that selectively sums the scaled I component of the received symbol with each of the predetermined, scaled I coefficients thereby generating a plurality of I sums;

a plurality of Q summing blocks that selectively sums the scaled Q component of the received symbol with each of the predetermined, scaled Q coefficients thereby generating a plurality of Q sums;

a plurality of I squaring blocks that squares each I sum of the plurality of I sums thereby generating a plurality of squared I sums;

a plurality of Q squaring blocks that squares each Q sum of the plurality of Q sums thereby generating a plurality of squared Q sums;

a square output multiplexor that receives the plurality of squared I sums and the plurality of squared Q sums and outputs a plurality of I outputs and a plurality of Q outputs;

a plurality of I,Q summing blocks that selectively sums the plurality of I outputs and the plurality of Q outputs from the square output multiplexor according to the rate control sequence thereby generating a plurality of I,Q outputs;

a plurality of min* processing blocks that processes the plurality of I,Q outputs thereby generating a plurality of output metrics according to the rate control sequence; and

a metric output multiplexor that selects an output metric from the plurality of output metrics according to the rate control sequence.

36. The metric generator of claim 35, wherein the rate control sequence comprises a plurality of modulations;

and

each modulation of the plurality of modulations comprises a constellation and a mapping.

37. The metric generator of claim 36, wherein:

the plurality of predetermined, scaled I coefficients and the plurality of predetermined, scaled Q coefficients comprise symmetry along I and Q axes of the constellation;

the plurality of I summing blocks selectively sums the scaled I component of the received symbol with each of the predetermined, scaled I coefficients by employing the symmetry; and

the plurality of Q summing blocks selectively sums the scaled Q component of the received symbol with each of the predetermined, scaled Q coefficients by employing the symmetry.

38. The metric generator of claim 36, wherein one modulation of the plurality of modulations comprises at least one of 8 Phase Shift Keying (PSK) modulation, Quadrature Phase Shift Keying (QPSK) modulation, 16 Quadrature Amplitude Modulation (QAM), and 16 Amplitude Phase Shift Keying (APSK) modulation.

39. The metric generator of claim 35, further comprising a plurality of at least one of mm processing blocks, max processing blocks, and max* processing blocks that processes the plurality of I,Q outputs thereby generating the plurality of output metrics according to the rate control sequence.

40. The metric generator of claim 35, wherein the square output multiplexor employs a look up table that comprises a plurality of predetermined square output MUX selections defined according to the rate control sequence.

41. The metric generator of claim 35, wherein the metric output multiplexor employs a look up table that comprises a plurality of predetermined metric output MUX selections defined according to the rate control sequence.

42. The metric generator of claim 35, wherein the metric generator is contained within a turbo trellis coded modulation (TTCM) decoder.

43. The metric generator of claim 42, wherein the TTCM decoder comprises a variable code rate TTCM decoder.

44. The metric generator of claim 35, wherein the metric generator is contained within at least one of a satellite receiver, a high definition television (HDTV) set top box receiver, a mobile receiver, a base station receiver, a receiver, and a transceiver.

45. The metric generator of claim 35, wherein the metric generator is contained within a decoder that decodes information that is received at a rate greater than substantially 80 mega-bits per second.

46. The metric generator of claim 35, wherein the received symbol is encoded using a systematic encoder.

47. The metric generator of claim 35, wherein the received symbol is encoded using a non-systematic encoder.

48. A metric generator method that calculates a metric associated with a received symbol according to a rate control sequence, the method comprising:

calculating a plurality of in-phase (I) sums using an I component of a received symbol and a plurality of predetermined I coefficients;

calculating a plurality of quadrature (Q) sums using a Q component of the received symbol and a plurality of predetermined Q coefficients;

squaring each I sum of the plurality of I sums;

squaring each Q sum of the plurality of Q sums;

selectively summing an I sum of the plurality of I sums with a Q sum of the plurality of Q sums thereby generating a plurality of I,Q outputs according to the rate control sequence;

performing min* processing on the plurality of I,Q outputs to generate a plurality of output metrics according to the rate control sequence; and

outputting one metric from the plurality of output metrics according to the rate control sequence.

49. The method of claim 48, further comprising performing variance factor scaling on the plurality of I,Q outputs based on a signal to noise ratio of the received symbol.

50. The method of claim 48, further comprising performing sigma factor scaling on the I component of the received symbol and the Q component of the received symbol based on a signal to noise ratio of the received symbol.

51. The method of claim 48, further comprising performing sigma factor scaling on the plurality of predetermined I coefficients and the plurality of predetermined Q coefficients based on a signal to noise ratio of the received symbol.

52. The method of claim 48, further comprising performing sigma factor scaling on the plurality of I sums and the plurality of Q sums based on a signal to noise ratio of the received symbol.

53. The method of claim 48, wherein the rate control sequence comprises a plurality of modulations;

and

each modulation of the plurality of modulations comprises a constellation and a mapping.

54. The method of claim 53, wherein:

the plurality of predetermined I coefficients and the plurality of predetermined Q coefficients comprise symmetry along I and Q axes of the constellation; and

further comprising employing the symmetry when calculating the plurality of I sums and when calculating the plurality of Q sums.

55. The method of claim 53, wherein one modulation of the plurality of modulations comprises at least one of 8 Phase Shift Keying (PSK) modulation, Quadrature Phase Shift Keying (QPSK) modulation, 16 Quadrature Amplitude Modulation (QAM), and 16 Amplitude Phase Shift Keying (APSK) modulation.

56. The method of claim 53, further comprising performing min* processing on the plurality of I,Q outputs to generate the plurality of plurality of output metrics according to the rate control sequence.

57. The method of claim 53, wherein the method is performed within a turbo trellis coded modulation (TTCM) decoder.

58. The method of claim 57, wherein the TTCM decoder comprises a variable code rate TTCM decoder.

59. The method of claim 53, wherein the method is performed within at least one of a satellite receiver, a high definition television (HDTV) set top box receiver, a mobile receiver, a base station receiver, a receiver, and a transceiver.

60. The metric generator of claim 48, wherein the metric generator is contained within a decoder that decodes information that is received at a rate greater than substantially 80 mega-bits per second.

61. The metric generator of claim 48, wherein the received symbol is encoded using a systematic encoder.

62. The metric generator of claim 48, wherein the received symbol is encoded using a non-systematic encoder.