Smart label and a smart label web

• US 7,066,393 B2
• Filed: 11/17/2003
• Issued: 06/27/2006
• Est. Priority Date: 05/31/2001
• Status: Expired due to Fees

• Current Assignee: SMARTRAC Investment B.V. (Avery Dennison Corporation)
• Original Assignee: Rafsec Oy
• Inventors: Strömberg, Samuli, Hanhikorpi, Marko
• Primary Examiner(s): Stcyr, Daniel
• Assistant Examiner(s): Hess, Daniel A.
• Application Number:
  US10/715,012
• Publication Number:
  US 20040169586A1
• Time in Patent Office: 953 Days
• Field of Search: 235/487, 235/492, 361/737, 361/761
• US Class Current: 235/492
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/0775 arrangements for connecting the integrated circuit to the antenna

Abstract

A smart label comprises a circuitry pattern on a smart label substrate and a structural part comprises an integrated circuit on a chip on a structural part substrate. The structural part is attached to the smart label substrate and/or the circuitry pattern. The circuitry pattern is electrically connected to the integrated circuit on the chip via at least one capacitor located outside the chip.

Claims

1. A smart label comprising a circuitry pattern and at least one capacitor plate on a smart label substrate, and a structural part comprising an integrated circuit on a chip and at least one capacitor plate on a structural part substrate, the structural part substrate being substantially smaller than the smart label substrate and being attached to the smart label substrate in such a manner that the capacitor plate on the smart label substrate and the capacitor plate on the structural part substrate are aligned thereby electrically connecting the circuitry pattern and the integrated circuit on the chip through a dielectric layer between the capacitor plates wherein the structural part is attached to the smart label substrate on the side opposite to the side where the circuitry pattern is located and the dielectric layer comprises the smart label substrate.

2. The smart label according to claim 1, wherein the integrated circuit on the chip is connected to the circuitry pattern via two capacitors connected in series and located outside the chip.

3. The smart label according to claim 2, wherein the smart label substrate has a dissipation factor of not more than 0.7×

10<sup>−

3</sup>.

4. The smart label according to claims 1 or 3, wherein the material of the smart label substrate is polyolefin.

5. The smart label according to claim 4, wherein the polyolefin is selected from the group consisting of polypropylene and polyethylene.

6. The smart label according to claim 1, wherein the structural part comprising the integrated circuit on the chip is attached to the smart label by means of a thermoplastic material.

7. The smart label according to claim 6, wherein the thermoplastic material is an anisotropic conductive thermoplastic film.

8. The smart label according to claim 1 or 6, wherein the integrated circuit on the chip is located between the thermoplastic material and the smart label substrate.

9. The smart label according to claim 1, wherein the material of the structural part substrate is selected from the group consisting of polyimide and polyester.

10. A smart label web comprising smart labels one after another andlor side by side, the smart label comprising a circuitry pattern and at least one capacitor plate on a smart label substrate and a structural part comprising an integrated circuit on a chip, and at least one capacitor plate on a structural part substrate, the structural part substrate being substantially smaller than the smart label substrate and being attached to the smart label substrate in such a manner that the capacitor plate on the smart label substrate and the capacitor plate on the structural part substrate are aligned thereby electrically connecting the circuitry pattern and the integrated circuit on the chip through a dielectric layer between the capacitor plates wherein the structural part is attached to the smart label substrate on the same side where the circuitry pattern is located and the dielectric layer comprises a printed isolation layer.

11. The smart label web according to claim 10, wherein the integrated circuit on the chip is connected to the circuitry pattern via two capacitors connected in series and located outside the chip.

12. A smart label comprising a circuitry pattern on a smart label substrate;

and

a structural part, the structural part comprising a thermoplastic film, a base web, and an integrated circuit on a chip on the thermoplastic film, the structural part being attached to the smart label substrate, and the circuitry pattern being electrically connected to the integrated circuit on the chip by at least one capacitor outside the chip, at least one capacitor plate of the at least one capacitor on the smart label substrate opposing at least one capacitor plate of the at least one capacitor on the surface of the base web of the structural part, at least one of the opposing plates being larger than its opposite plate, the structural part smaller than the smart label substrate wherein the integrated circuit on the chip is connected to the circuitry pattern via two capacitors connected in series and located outside the chip and wherein the structural part is attached to the smart label substrate on the side opposite to the side where the circuitry pattern is located, and the dielectric layer comprises the smart label substrate.

13. The smart label according to claim 12, wherein the thermoplastic film material is an anisotropically conductive.

14. The smart label according to claim 13, wherein the capacitor comprises capacitor plates which are formed on the smart label substrate and the structural part substrate, the anisotropically conductive thermoplastic film on the same side of the smart label substrate where the circuitry pattern is located and is isolated from the circuitry pattern.

15. The smart label according to claim 13, wherein the capacitor comprises capacitor plates which are formed on the smart label substrate and the structural part substrate, the smart label substrate forming a dielectric layer between the capacitor plates.

16. The smart label according to claim 12, wherein the smart label substrate has a dissipation factor of not more than 0.7×

10<sup>−

3</sup>.

17. The smart label according to claims 12 or 16, wherein the material of the smart label substrate is polyolefin.

18. The smart label according to claims claim 12 wherein the structural part comprising the integrated circuit on the chip is attached to the smart label by the thermoplastic film.

19. The smart label according to claim 12, wherein the base web of the structural part comprises material selected from the group consisting of polyimide and polyester.

20. The smart label according to claim 18, wherein the integrated circuit on the chip is located between the thermoplastic material and the smart label substrate.