Package having bond-sealed underbump

• US 7,067,355 B2
• Filed: 05/26/2004
• Issued: 06/27/2006
• Est. Priority Date: 05/26/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Haluzak, Charles C., Truninger, Martha A., Michael, Donald L.
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US10/854,110
• Publication Number:
  US 20050275072A1
• Time in Patent Office: 762 Days
• Field of Search: 438/116
• US Class Current: 438/116
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate

Abstract

A package for containing microelectromechanical devices includes a first substrate wafer, and a second substrate wafer made of an optical quality material. An underbump is interposed between the first and second substrate wafers. The underbump is composed of a standoff region and a localized bond region. The first and second substrate wafers and the underbump define a chamber that contains at least one microelectronic device.

Claims

1. A method for fabricating an electronic device package structure comprising the steps of:

establishing an underbump on a first substrate wafer, the underbump composed of a localized bond region and standoff material having a face distal to the first substrate wafer, the localized bond region deposited on the distal face of the standoff material;

preparing at least one breach cut in the underbump; and

then adhering the first substrate wafer having the underbump positioned thereon to a second substrate wafer, thereby defining a chamber adapted to contain the electronic device therein;

wherein the breach cut extends from an exterior surface of the underbump to the chamber.

2. The method of claim 1 wherein establishing the underbump comprises:

establishing the standoff material on the first substrate wafer;

depositing at least one bond material layer over the standoff material, thereby forming a stack; and

configuring the stack into an underbump.

3. The method of claim 2, further comprising the step of establishing an adhesion layer over the standoff material prior to establishing the at least one bond material layer.

4. The method of claim 3 wherein the adhesion layer is selected from tantalum, a tantalum-containing compound, and combinations thereof, and the at least one bond material layer includes at least one layer containing tin and at least one layer containing gold.

5. The method of claim 1 wherein adhering comprises one of anodically bonding and soldering the localized bond region of the underbump to the second substrate wafer.

6. The method of claim 1 wherein the material is selected from tetra-orthosilicate glass, silica glass, phosphosilicate, polysilicon, borosilicate glass, titanium silicate glass, polysilazane, tetraethyl-ortho-silicate glass, metal-organic spin-on coatings, nickel, copper, and mixtures thereof.

7. The method of claim 1 wherein the localized bond region is a metal material, and the method further comprises depositing the metal material on the underbump and the breach cut prior to adhering the underbump to the second substrate wafer.

8. The method of claim 1, further comprising hermetically sealing the breach cut by soldering after adhering the underbump to the second substrate wafer.

9. The method of claim 1, further comprising depositing a protective layer on the first substrate wafer, the protective layer positioned on a face of the first substrate wafer opposed to the underbump, the protective layer deposited prior to establishing the underbump.

10. The method of claim 9 wherein the first substrate wafer is optical quality glass and the standoff material is selected from tetraethyl orthosilicate, polysilicon glass, and combinations thereof.

11. A method for fabricating an electronic device package structure comprising the steps of:

establishing a standoff material on a first substrate wafer;

establishing an adhesion layer over the standoff material, wherein the adhesion layer is selected from tantalum, a tantalum-containing compound, and combinations thereof;

then depositing at least one bond material lever over the adhesion layer, thereby forming a stack, wherein the at least one bond material layer includes at least one layer containing tin and at least one layer containing gold;

configuring the stack into an underbump by;

masking the stack with at least one resist material;

sequentially etching the adhesion layer and the at least one bond material layer into an underbump pattern;

masking the standoff material after the at least one bond material layer has been etched; and

etching the standoff material into the underbump pattern; and

adhering the first substrate wafer having the underbump positioned thereon to a second substrate wafer, thereby defining a chamber adapted to contain the electronic device therein.

12. A method for fabricating an electronic device package structure comprising the steps of:

establishing a standoff material on a first substrate wafer;

depositing at least one bond material layer over the standoff material, thereby forming a stack;

configuring the stack into an underbump by;

masking the stack with at least one resist material;

etching the at least one bond material layer into an underbump pattern;

masking the standoff material after the at least one bond material layer has been etched; and

etching the standoff material into the underbump pattern; and

adhering the first substrate wafer having the underbump positioned thereon to a second substrate wafer, thereby defining a chamber adapted to contain the electronic device therein.

13. A method for fabricating an electronic device package structure comprising the steps of:

establishing an underbump on a first substrate wafer, the underbump composed of a localized bond region deposited in overlying relationship to a standoff material;

adhering the first substrate wafer having the underbump positioned thereon to a second substrate wafer, thereby defining a chamber adapted to contain the electronic device therein;

depositing a protective layer on the first substrate wafer, the protective layer positioned on a face of the first substrate wafer opposed to the underbump, the protective layer deposited prior to establishing the underbump;

removing the protective layer subsequent to establishing the underbump; and

depositing an anti-reflective coating an the face of the first substrate wafer after removing the protective layer.