High voltage power MOSFET having low on-resistance

• US 7,067,376 B2
• Filed: 09/29/2003
• Issued: 06/27/2006
• Est. Priority Date: 06/02/2000
• Status: Expired due to Term

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A.
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Le, Thao X.
• Application Number:
  US10/673,889
• Publication Number:
  US 20040070044A1
• Time in Patent Office: 1,002 Days
• Field of Search: 438268-271, 438/589, 438/44, 438/245, 438/360, 438/388, 438/429, 438/14, 438/17, 438/138, 257/496, 257/491, 257/341, 257/331, 257/339, 257/E29.26
• US Class Current: 438/268
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with an epitaxially layered material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.

Claims

1. A method of forming a power MOSFET comprising the steps of:

providing a substrate of a first conductivity type;

depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

forming first and second body regions in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type;

forming first and second source regions of the first conductivity type in the first and second body regions, respectively; and

forming a plurality of trenches in said drift region of the epitaxial layer;

epitaxially depositing in said trenches a material having a dopant of the second conductivity type, said trenches extending toward the substrate from the first and second body regions; and

diffusing at least a portion of said dopant from said trenches into portions of the epitaxial layer adjacent the trenches;

said epitaxially deposited material filling the trench includes silicon; and

further comprising the step of forming a layer of dielectric on the epitaxially deposited material filling the trench.

2. The method of claim 1 wherein said dopant is boron.

3. The method of claim 1 further comprising the step of forming a layer of thermal oxide on the epitaxial layer of silicon deposited in the trench.

4. The method of claim 1 wherein a layer of epitaxial silicon is deposited on the original trench walls and a layer of dielectric is formed on said epitaxial layer, thereby filling the trench.

5. The method of claim 1 wherein said body regions include deep body regions that are deeper than the first body region but shallower than p-type regions formed around the trenches.

6. The method of claim 1, wherein said trench is formed by providing a masking layer defining at least one trench, and etching the trench defined by the masking layer.

7. The method of claim 1, wherein said body region is formed by implanting and diffusing a dopant into the substrate.

8. The method of claim 1 wherein the epitaxially depositing step includes the step of epitaxially depositing a plurality of layers, at least two of said layers having different dopant concentrations.

9. The method of claim 8 wherein said plurality of layers includes an interface layer adjacent to one of the body regions, said interface layer having a lower dopant concentration than an interior layer of the epitaxially layered material.

10. The method of claim 1 wherein said epitaxially layered material has a dopant concentration that is reduced in the vicinity of the body regions relative to the dopant concentration profile in the vicinity of the substrate.

11. The method of claim 1 wherein said portions of the epitaxial layer adjacent the trenches have a substantially uniform dopant concentration in a direction lateral to the trenches, and have an opposite doping type to that of the epitaxial layers deposited on the substrate.

12. The method of claim 10 wherein said portions of the epitaxial layer adjacent the trenches have a substantially uniform dopant concentration in a direction lateral to the trenches, and have an opposite doping type to that of the epitaxial layers deposited on the substrate.

13. A power MOSFET made in accordance with the method of claim 1.