Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same

• US 7,067,856 B2
• Filed: 02/02/2004
• Issued: 06/27/2006
• Est. Priority Date: 02/10/2000
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Droopad, Ravindranath, Hilt, Lyndee L., Ramdani, Jamal, Eisenbeiser, Kurt Williamson
• Primary Examiner(s): Booth, Richard A.
• Application Number:
  US10/768,108
• Publication Number:
  US 20040149203A1
• Time in Patent Office: 876 Days
• Field of Search: 257/190, 257/200, 257/201
• US Class Current: 257/190
• CPC Class Codes: C30B 25/18 characterised by the substrate
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02439 Materials
• CPC Class Codes: H01L 21/02472 Oxides
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02543 Phosphides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02557 Sulfides
• CPC Class Codes: H01L 21/0256 Selenides
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 : integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/15 : including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/16 : with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
• CPC Class Codes: H01L 33/30 : containing only elements of Group III and Group V of the Periodic Table
• CPC Class Codes: H01S 5/021 : Silicon based substrates
• CPC Class Codes: H01S 5/0261 : Non-optical elements, e.g. laser driver components, heaters H01S5/0265 takes precedence

Abstract

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Claims

1. A semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material in contact with the monocrystalline silicon substrate;

a monocrvstalline metal oxide selected from the group consisting of alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, gadolinium oxide and mixtures thereof contacting the amorphous oxide material; and

a monocrystalline compound semiconductor material overlying the monocrystalline metal oxide.

2. The semiconductor structure of claim 1 wherein the monocrystalline silicon substrate is orientated in the (100) direction.

3. The semiconductor structure of claim 1 further comprising a template layer formed between the monocrystalline metal oxide and the monocrystalline compound semiconductor material.

4. The semiconductor structure of claim 1 further comprising a buffer material of monocrystalline semiconductor material formed between the monocrystalline metal oxide and the monocrystalline compound semiconductor material.

5. The semiconductor structure of claim 4 further comprising a template layer formed between the monocrystalline metal oxide and the buffer material.

6. The semiconductor structure of claim 4 wherein the buffer material is selected from the group consisting of. Germanium, a GaAs_xP₁₋

x, superlattice where x ranges from 0 to 1, an In_yGa<sub>1−

y</sub>P superlattice where y ranges from 0to 1, and an InGaAs superlattice.

7. The semiconductor structure of claim 1 wherein the monocrystalline metal oxide comprises Sr_zBa₁₋

zTiO₃ wherein z ranges from 0to 1.

8. The semiconductor structure of claim 1 wherein the monocrystalline compound semiconductor material is selected from the group consisting of:

III–

V compounds, mixed III-V compounds, II–

VI compounds, and mixed II-VI compounds.

9. The semiconductor structure of claim 1 wherein the monocrystalline compound semiconductor material is selected from the group consisting of:

GaAs, AlGaAS, Inp, InGaAs, InGaP, ZnSe, AllnAs, CdS, CdHgTe, and ZnSeS.