Double gate device having a heterojunction source/drain and strained channel

• US 7,067,868 B2
• Filed: 09/29/2004
• Issued: 06/27/2006
• Est. Priority Date: 09/29/2004
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Zhang, Da, Kolagunta, Venkat R., Thean, Voon-Yew, Nguyen, Bich-Yen, White, Ted R., Vartanian, Victor H., Barr, Alexander L., Sadaka, Mariam G.
• Primary Examiner(s): Owens, Douglas W.
• Application Number:
  US10/952,676
• Publication Number:
  US 20060065927A1
• Time in Patent Office: 636 Days
• Field of Search: 257/296, 257/327, 257/347, 257/368
• US Class Current: 257/296
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

Claims

1. A semiconductor device, comprising:

a semiconductor layer;

a first gate dielectric adjacent a first side of a first portion of the semiconductor layer;

a first gate electrode adjacent the first gate dielectric;

a second gate dielectric adjacent a second side of the first portion of the semiconductor layer;

a second gate electrode adjacent the second gate dielectric;

means for encapsulating at least one of (i) the first gate electrode and the first gate dielectric and (ii) the second gate electrode and the second gate dielectric;

a strained channel region having first and second heterojunctions adjacent opposite ends of the strained channel region and within the first portion of the semiconductor layer; and

a semiconductor material selectively grown overlying a second portion of the semiconductor layer outside the first portion, wherein the semiconductor material comprises a material different from a material of the semiconductor layer, and wherein the semiconductor material is used as a diffusion source by controlling an amount of diffusion of the semiconductor material into the strained channel region of the first and second portions of the semiconductor layer.

2. The semiconductor device of claim 1, further comprising:

source/drain extension regions within the semiconductor layer;

at least one sidewall spacer adjacent one or mate of the first gate electrode and the second gate electrode, the at least one sidewall spacer further being disposed adjacent the source/drain extension regions; and

source/drain regions adjacent the source/drain extension regions and within the semiconductor layer.

3. The semiconductor device of claim 2, further comprising:

silicided regions of the source/drain regions and at least one of the first gate electrode and the second gate electrode.

4. The semiconductor device of claim 1, wherein the semiconductor material includes at least one selected from the group consisting of a source of germanium atoms and carbon doped silicon.

5. The semiconductor device of claim 1, further comprising:

source/drain extension regions within the semiconductor layer;

sidewall spacers adjacent the first gate electrode, the sidewall spacers adjacent the source/drain extension regions;

source/drain regions adjacent the source/drain extension regions within the semiconductor layer; and

silicided regions of the source/drain regions and the first gate electrode.

6. The semiconductor device of claim 1, wherein the semiconductor layer includes a semiconductor layer of a semiconductor on insulator substrate.

7. The semiconductor device of claim 6, wherein the semiconductor on insulator substrate includes a silicon on insulator substrate.

8. The semiconductor device of claim 1, wherein the means for encapsulating includes an encapsulant for minimizing oxygen diffusion into at least one of (i) the first gate electrode and the first gate dielectric and (ii) the second gate electrode and the second gate dielectric.

9. The semiconductor device of claim 1, wherein the means for encapsulating includes an encapsulatant selected from the group consisting of nitride, oxide, and a combination of nitride and oxide.

10. The semiconductor device of claim 1, wherein the semiconductor material includes at least one selected from the group consisting of a source of germanium, carbon doped silicon, boron, phosphorus and arsenic.

11. The semiconductor device of claim 10, further wherein for a given thickness of the semiconductor material, the desired Ge concentration is inversely proportional to the given thickness, and a function of an oxidation time, in order to preserve a total amount of Ge to be diffused into the first portion and the second portion of the semiconductor layer.

12. The semiconductor device of claim 10, further wherein the desired Ge concentration is greater than 15%.

13. The semiconductor device of claim 1, wherein the semiconductor material is diffused vertically into the second portion of the semiconductor layer and further diffused laterally within the first portion of the semiconductor layer to a source/channel interface and a drain/channel interface to form heterojunctions at respective interfaces of the strained channel region.

14. The semiconductor device of claim 1, wherein the semiconductor device includes one selected from the group consisting of a lateral FET device and a FinFET.

15. A semiconductor device, comprising:

a semiconductor layer;

a first gate dielectric adjacent a first side of a first portion of the semiconductor layer;

a first gate electrode adjacent the first gate dielectric;

a second gate dielectric adjacent a second side of the first portion of the semiconductor layer;

a second gate electrode adjacent the second gate dielectric;

means for encapsulating at least one of (i) the first gate electrode and the first gate dielectric and (ii) the second gate electrode and the second gate dielectric;

a strained channel region having first and second heterojunctions adjacent opposite ends of the strained channel region and within the first portion of the semiconductor layer;

a semiconductor material selectively grown overlying a second portion of the semiconductor layer outside the first portion, wherein the semiconductor material comprises a material different from a material of the semiconductor layer, and wherein the semiconductor material is used as a diffusion source by controlling an amount of diffusion of the semiconductor material into the strained channel region of the first and second portions of the semiconductor layer;

source/drain extension regions within the semiconductor layer;

at least one sidewall spacer adjacent one or more of the first gate electrode and the second gate electrode, the at least one sidewall spacer further being disposed adjacent the source/drain extension regions; and

source/drain regions adjacent the source/drain extension regions and within the second portion of the semiconductor layer.

16. The semiconductor device of claim 15, wherein the semiconductor material is diffused vertically into the second portion of the semiconductor layer and further diffused laterally within the first portion of the semiconductor layer to a source/channel interface and a drain/channel interface to form heterojunctions at respective interfaces of the strained channel region.

17. The semiconductor device of claim 15, wherein the semiconductor device includes one selected from the group consisting of a lateral FET device and a FinFET.