Semiconductor device including trench with at least one of an edge of an opening and a bottom surface being round

• US 7,067,874 B2
• Filed: 05/13/2003
• Issued: 06/27/2006
• Est. Priority Date: 02/04/1994
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nakamura, Katsumi, Minato, Tadaharu, Shiozawa, Katsuomi, Tominaga, Shuuichi
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US10/436,084
• Publication Number:
  US 20030203573A1
• Time in Patent Office: 1,141 Days
• Field of Search: 257/506, 257/510, 257328-330, 438/259, 438/270, 438/271, 438/589
• US Class Current: 257/330
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66356 Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
• CPC Class Codes: H01L 29/66378 the other device being a controlling field-effect device
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7824 : with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device that includes an insulating substrate, a plurality of semiconductor layers arranged to be isolated from one another on the insulating substrate, and a semiconductor element independently provided on the semiconductor layers. Further, a trench may extend from the main surface to the substrate and have an inner wall covered with an insulating film. At least one of an edge on the side of the substrate and an edge on the side opposite thereof of the semiconductor layer has a rounded surface. Further, an angle between a line tangent to a surface having a smallest radius of curvature of the rounded surface of the edge and the main surface ranges from 30° to 60° at a section of the edge.

Claims

1. A semiconductor device, comprising:

an insulating substrate;

a semiconductor layer provided on said substrate and having a main surface on a side opposite to said substrate;

a trench extending from said main surface to said substrate and having an inner wall covered with an insulating film; and

a semiconductor element formed in said semiconductor layer,

wherein an edge of an opening of said trench and a bottom surface of said trench have rounded surfaces,

wherein said rounded surface of said bottom surface is a widened portion of said trench wider than said inner wall of said trench, such that said bottom surface of said trench is concave to an outside of said trench.

2. The semiconductor device according to claim 1, wherein

said semiconductor layer includes a plurality of semiconductor layers, said semiconductor element includes a plurality of semiconductor elements, and each said semiconductor element respectively formed in said semiconductor layers adjacently provided to each other is isolated from each other by said trench intervening between said semiconductor layers.

4. The semiconductor device according to claim 1, wherein

an angle between a line tangent to a surface having a smallest radius of curvature among radiuses of curvature of said rounded surface of said edge of said opening of said trench and said main surface ranges from 30°

to 60°

at a section of said edge of said opening of said trench.

5. The semiconductor device according to claim 4, wherein

an angle between a line tangent to a surface having a smallest radius of curvature among radiuses of curvature of said rounded surface of said edge on said side opposite to said substrate and a main surface of said semiconductor layer ranges from 30°

to 60°

at a section of said edge on said side opposite to said substrate.

3. A semiconductor device, comprising:

an insulating substrate;

a plurality of semiconductor layers arranged to be isolated from one another on said substrate; and

a semiconductor element independently provided in said semiconductor layers,

wherein an edge on a side of said substrate, an edge of said semiconductor layer on a side opposite of said side of said substrate, and a bottom surface of a trench in said substrate have rounded surfaces,

said rounded surface of said edge on said side of said semiconductor layer is convex to an outside of said semiconductor layer, and

said rounded surface of said bottom surface is a widened portion of said trench wider than an inner wall of said trench, such that said bottom surface of said trench is concave to an outside of said trench.