Semiconductor device

• US 7,067,881 B2
• Filed: 01/12/2004
• Issued: 06/27/2006
• Est. Priority Date: 01/15/2003
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Matsumoto, Takuji, Iwamatsu, Toshiaki, Ipposhi, Takashi, Hirano, Yuuichi
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US10/754,539
• Publication Number:
  US 20040227185A1
• Time in Patent Office: 897 Days
• Field of Search: None
• US Class Current: 257/347
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate

Abstract

A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.

Claims

1. A semiconductor device comprising:

an SOI substrate having a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type that are stacked in this order;

element isolation insulating films formed partially in a main surface of said semiconductor layer, with portions of said semiconductor layer interposed between said insulating layer and bottom surfaces of said element isolation insulating films;

a gate structure formed partially on said main surface of said semiconductor layer in an element formation region defined by said element isolation insulating films;

a pair of recesses formed in said element formation region, said recesses being formed in said main surface of said semiconductor layer in portions that are not covered by said gate structure, with a channel formation region under said gate structure interposed between said pair of recesses; and

source/drain regions formed in bottom surfaces of said recesses and having a second conductivity type that is different from said first conductivity type, said source/drain regions forming a pair, with said channel formation region interposed therebetween, and having bottom surfaces or depletion layers that reach said insulating layer,

wherein the part of said main surface of said semiconductor layer on which said gate structure resides forms an angle larger than 90°

with a corresponding side surface of each said recess.

2. A semiconductor device comprising:

an SOI substrate having a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type that are stacked in this order;

element isolation insulating films formed partially in a main surface of said semiconductor layer, with portions of said semiconductor layer interposed between said insulating layer and bottom surfaces of said element isolation insulating films;

a gate structure formed partially on said main surface of said semiconductor layer in an element formation region defined by said element isolation insulating films;

a pair of recesses formed in said element formation region, said recesses being formed in said main surface of said semiconductor layer in portions that are not covered by said gate structure, with a channel formation region under said gate structure interposed between said pair of recesses; and

source/drain regions formed in bottom surfaces of said recesses and having a second conductivity type that is different from said first conductivity type, said source/drain regions forming a pair, with said channel formation region interposed therebetween, and having bottom surfaces or depletion layers that reach said insulating layer,

wherein said source/drain regions comprise;

first impurity-introduced regions having a relatively low concentration and formed in said main surface of said semiconductor layer; and

second impurity-introduced regions having a relatively high concentration and formed deeper than said first impurity-introduced regions,

wherein a depth from said main surface of said semiconductor layer to said bottom surface of each said recess is smaller than a depth from said main surface of said semiconductor layer to a bottom surface of each said first impurity-introduced region.

3. The semiconductor device according to claim 2,

wherein said source/drain regions further comprise third impurity-introduced regions formed in said main surface of said semiconductor layer, reaching a depth shallower than a depth of said second impurity-introduced regions.

4. A semiconductor device comprising:

an SOI substrate having a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type that are stacked in this order;

element isolation insulating films formed partially in a main surface of said semiconductor layer, with portions of said semiconductor layer interposed between said insulating layer and bottom surfaces of said element isolation insulating films;

a gate structure formed partially on said main surface of said semiconductor layer in an element formation region defined by said element isolation insulating films;

a pair of recesses formed in said element formation region, said recesses being formed in said main surface of said semiconductor layer in portions that are not covered by said gate structure, with a channel formation region under said gate structure interposed between said pair of recesses; and

source/drain regions formed in bottom surfaces of said recesses and having a second conductivity type that is different from said first conductivity type, said source/drain regions forming a pair, with said channel formation region interposed therebetween, and having bottom surfaces or depletion layers that reach said insulating layer,

wherein said source/drain regions comprise;

first impurity-introduced regions having a relatively low concentration and formed in said main surface of said semiconductor layer;

second impurity-introduced regions having a relatively high concentration and formed deeper than said first impurity-introduced regions; and

third impurity-introduced regions formed in said main surface of said semiconductor layer,

wherein a depth from said main surface of said semiconductor layer to bottom surfaces of said third impurity-introduced regions is greater than a depth from said main surface of said semiconductor layer to bottom surfaces of said first impurity-introduced regions, and

wherein a depth from said main surface of said semiconductor layer to said bottom surfaces of said recesses is smaller than a depth from said main surface of said semiconductor layer to said bottom surfaces of said third impurity-introduced regions.

5. A semiconductor device comprising:

an SOI substrate having a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type that are stacked in this order;

element isolation insulating films formed partially in a main surface of said semiconductor layer, with portions of said semiconductor layer interposed between said insulating layer and bottom surfaces of said element isolation insulating films;

a gate structure formed partially on said main surface of said semiconductor layer in an element formation region defined by said element isolation insulating films;

a pair of recesses formed in said element formation region, said recesses being formed in said main surface of said semiconductor layer in portions that are not covered by said gate structure, with a channel formation region under said gate structure interposed between said pair of recesses; and

source/drain regions formed in bottom surfaces of said recesses and having a second conductivity type that is different from said first conductivity type, said source/drain regions forming a pair, with said channel formation region interposed therebetween, and having bottom surfaces or depletion layers that reach said insulating layer,

wherein said gate structure comprises;

a gate insulating film formed on said main surface of said semiconductor layer;

a gate electrode formed on said gate insulating film; and

first sidewalls formed on sides of said gate electrode; and

wherein said semiconductor device further comprises;

second sidewalls formed on said bottom surfaces of said recesses and in contact with said first sidewalls; and

metal-semiconductor compound layers formed on said source/drain regions in portions that are not covered by said second sidewalls.

6. The semiconductor device according to claim 5, further comprising third sidewalls formed on said bottom surfaces of said recesses and being in contact with said element isolation insulating films,

wherein said metal-semiconductor compound layers are formed on said source/drain regions in portions that are not covered by said second and third sidewalls.