Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage

• US 7,067,886 B2
• Filed: 11/04/2003
• Issued: 06/27/2006
• Est. Priority Date: 11/04/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Hook, Terence B., Bonges, Henry A. III, Lai, Wing L., Harmon, David L.
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US10/605,888
• Publication Number:
  US 20050093072A1
• Time in Patent Office: 966 Days
• Field of Search: 257/356, 257/357, 257/359, 257/360, 257/361
• US Class Current: 257/360
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

A method and structure alters an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.

Claims

1. A protection circuit for an integrated circuit device that includes silicon over insulator (SOI) transistors, wherein said protection circuit comprises:

a shunt connected to at least one of the source/drain and gate of at least one SOI transistor; and

a compensating conductor connected to said shunt,

wherein said shunt and said compensating conductor eliminate the potential for charging damage to the gate insulator of said SOI transistor, and

wherein said shunt and said compensating conductor perform no function other than eliminating said potential for charging damage.

2. The circuit in claim 1, wherein said shunt device is positioned in parallel with said SOI transistor.

3. The circuit in claim 1, further comprising a series device in place of said shunt.

4. The circuit in claim 3, wherein said series device is positioned between a first conductor connected to said SOI transistor and a second conductor that is not connected to said SOI transistor.

5. The circuit in claim 3, further comprising a second series device, wherein said series device is connected to a first conductor and said second series device is connected to a second conductor, and

wherein said first conductor is connected to said source/drain of said SOI transistor and said second conductor is connected to said gate of said SOI transistor.

6. A protection circuit for an integrated circuit device that includes silicon over insulator (SOI) transistors, wherein said protection circuit comprises:

a series device connected to at least one of the source/drain and gate of at least one SOI transistor; and

a compensating conductor connected to said series device,

wherein said series device and said compensating conductor eliminate the potential for charging damage between said source/drain and said gate of said SOI transistor, and

wherein said series device and said compensating conductor perform no function other than eliminating said potential for charging damage.

7. The circuit in claim 6, wherein said series device is positioned in parallel with said SOI transistor.

8. The circuit in claim 6, wherein said series device is positioned between a first conductor connected to said source/drain of said SOI transistor and a second conductor connected to said gate of said SOI transistor.

9. The circuit in claim 6, wherein said series device comprises a diode.

10. The circuit in claim 6, wherein said series device is positioned between a first conductor connected to said SOI transistor and a second conductor that is not connected to said SOI transistor.

11. The circuit in claim 6, further comprising a second series device, wherein said series device is connected to a first conductor and said second series device is connected to a second conductor, and

wherein said first conductor is connected to said source/drain of said SOI transistor and said second conductor is connected to said gate of said SOI transistor.

12. A protection circuit for au integrated circuit device that includes silicon over insulator (SOI) transistors, wherein said protection circuit comprises;

a shunt connected to at least one of the source/drain and gate of at least one SOI transistor; and

a first compensating conductor connected to said shunt;

a series device connected to at least one of the source/drain and gate of at least one SOI transistor, wherein said shunt and said series device are connected to different features of said at least one SOI transistor; and

a second compensating conductor connected to said series device,

wherein said shunt, said series device, said first compensating conductor, and said second compensating conductor eliminate the potential for charging damage to the gate insulator of said SOI transistor, and

wherein said shunt, said series device, said first compensating conductor, and said second compensating conductor perform no function other than eliminating said potential for charging damage.

13. The circuit in claim 12, wherein said shunt device is positioned in parallel with said SOI transistor.

14. The circuit in claim 12, wherein said shunt device is positioned between a third conductor connected to said SOI transistor and said fist compensating conductor that is not connected to said SOI transistor.

15. The circuit in claim 12, wherein said series device is positioned between a third conductor connected to said SOI transistor and said second compensating conductor that is not connected to said SOI transistor.