Multi-layer integrated semiconductor structure having an electrical shielding portion

• US 7,067,909 B2
• Filed: 12/30/2003
• Issued: 06/27/2006
• Est. Priority Date: 12/31/2002
• Status: Expired due to Fees

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Checka, Nisha, Chandrakasan, Anantha, Reif, Rafael
• Primary Examiner(s): Owens, Douglas W
• Application Number:
  US10/749,096
• Publication Number:
  US 20060087019A1
• Time in Patent Office: 910 Days
• Field of Search: 257/686, 257/777
• US Class Current: 257/686
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/8383 Solid-solid interdiffusion
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01016 : Sulfur [S]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01054 : Xenon [Xe]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A multi-layer integrated semiconductor structure is provided, which includes at least a first semiconductor structure and a second semiconductor structure coupled together via an interface. The interface includes at least a first portion adapted to provide a communication interface between the first semiconductor structure and the second semiconductor structure and at least a second portion adapted to reduce electrical interference between the first semiconductor structure and the second semiconductor structure.

Claims

1. A multi-layer integrated semiconductor structure, comprising:

a first semiconductor structure comprising a first surface and semiconductor elements associated with a first semiconductor signaling technology;

a second semiconductor structure comprising a second surface and semiconductor elements associated with a second semiconductor signaling technology; and

an interface disposed between the first surface and the second surface, the interface comprising a first portion adapted to provide a communication interface between the first and second semiconductor structures and a second portion adapted to reduce electrical interference between signals propagating along the first and second semiconductor structures, the second portion being directly coupled to the first surface and the second surface, at least one of the first and second interface portions corresponding to a conductive bonding interface which secures the first surface of the first semiconductor structure to the first surface of the second semiconductor structure.

2. The multi-layer integrated semiconductor structure of claim 1, wherein the first portion of the interface includes an electrically conductive adhesive material securing the first surface to the second surface.

3. The multi-layer integrated semiconductor structure of claim 1, wherein the first portion of the interface includes an electrically conductive material.

4. The multi-layer integrated semiconductor structure of claim 1, wherein the second portion of the interface includes an electrically conductive adhesive material.

5. The multi-layer integrated semiconductor structure of claim 4, wherein the electrically conductive adhesive material is grounded.

6. The multi-layer integrated semiconductor structure of claim 5, wherein the electrically conductive adhesive material includes at least one of copper, gold, aluminum or a metal alloy.

7. The multi-layer integrated semiconductor structure of claim 1, wherein the second portion of the interface includes a dielectric adhesive material.

8. The multi-layer integrated semiconductor structure of claim 7, wherein the dielectric adhesive material includes an organic material.

9. The multi-layer integrated semiconductor structure of claim 7, wherein the dielectric adhesive material includes an inorganic material.

10. The multi-layer integrated semiconductor structure of claim 1, wherein the first semiconductor signaling technology includes digital signaling related technology.

11. The multi-layer integrated semiconductor structure of claim 1, wherein the second semiconductor signaling technology includes analog signaling related technology.

12. The multi-layer integrated semiconductor structure of claim 1, wherein the first and second interface portions are provided from an electrically conductive adhesive adapted to adhesively couple the first surface to the second surface.

13. The multi-layer integrated semiconductor structure of claim 12, wherein the first surface corresponds to a top surface of the first semiconductor structure.

14. The multi-layer integrated semiconductor structure of claim 13, wherein the second surface corresponds to a bottom surface of the second semiconductor structure.

15. The multi-layer integrated semiconductor structure of claim 13, wherein the second surface corresponds to a top surface of the second semiconductor structure.

16. The multi-layer integrated semiconductor structure of claim 12, wherein the first surface corresponds to a bottom surface of the first semiconductor structure.

17. The multi-layer integrated semiconductor structure of claim 16, wherein the second surface corresponds to a top surface of the second semiconductor structure.

18. The multi-layer integrated semiconductor structure of claim 16, wherein the second surface corresponds to a bottom surface of the second semiconductor structure.

19. The multi-layer integrated semiconductor structure of claim 1, wherein both the first and second portions of said interface are provided from an electrically conductive bonding material.