Customizable and programmable cell array

• US 7,068,070 B2
• Filed: 10/06/2005
• Issued: 06/27/2006
• Est. Priority Date: 03/10/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Or-Bach, Zvi
• Primary Examiner(s): Le, Don P.
• Application Number:
  US11/244,108
• Publication Number:
  US 20060028242A1
• Time in Patent Office: 264 Days
• Field of Search: 326 38- 41, 257202-211
• US Class Current: 326/38
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H03K 19/1732 by limitation or reduction of the pin/gate ratio for data-processing equipment G06F1/22
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A semiconductor device may include a logic array having a multiplicity of inputs and a multiplicity of outputs and customized interconnections providing permanent direct interconnections among at least some of the multiplicity of inputs and at least some of the multiplicity of outputs.

Claims

1. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one flip-flop and at least one multiplexer, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein the connections between at least one of said multiplexers and one of said flip-flops are customized to create at least one flip-flop with synchronous enable.

2. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one flip-flop and at least one multiplexer, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein the connections between at least one of said multiplexers and one of said flip-flops are customized to create at least one flip-flop with synchronous preset.

3. A customizable logic array comprising:

an array of logic cell having a multiplicity of inputs and a multiplicity of outputs; and

customized interconnections permanently interconnecting at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs, wherein each of at least some of said logic cells comprises at least one flip-flop; and

a clock tree providing clock inputs to some of said flip-flops, wherein said clock tree comprises;

a clock input;

a clock signal;

an inverted clock signal; and

a power saving circuit.

4. A semiconductor device comprising:

a plurality of logic cells having a multiplicity of inputs and a multiplicity of outputs, wherein each of at least some of said logic cells comprises at least one flip-flop; and

a clock tree providing clock inputs to some of said flip-flops, wherein said clock tree comprises;

a clock input;

a clock signal;

an inverted clock signal;

a power saving circuit; and

control logic,

wherein said control logic provides a pulse to said power saving circuit on each transition of said clock input to short said clock signal and said inverted clock signal together.

5. A customizable logic array comprising:

an array of logic cells, having a multiplicity of inputs, a multiplicity of outputs, and at least one look up table with address decode;

a multiplicity of X decoders, each connected to a multiplicity of said look up table, with a multiplicity of word lines;

a multiplicity of Y decoders, each connected to a multiplicity of said look up table, with a multiplicity of bit lines; and

customized interconnections permanently interconnecting at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs, wherein

in a first state, said X decoders, said Y decoders, said word lines, said bit lines and said look up tables, function as a dual port memory; and

in a second state said Y decoders, said word lines and said bit lines function to program said look up tables.

6. The customizable logic array as in claim 5, wherein at least one said X decoder, said Y decoder, said bit line, said word line and said look up table function as a dual-port memory, while at least one other said look up table functions as logic.

7. A semiconductor device comprising:

an array of logic array including a multiplicity of logic cells, and metal connection layers overlying the multiplicity of logic cells for providing at least one permanent customized direct interconnect between various inputs and outputs thereof,

wherein each logic cell comprises;

at least one look-up table; and

at least one tristate inverter.

8. The semiconductor device as in claim 7, further comprising:

a multiplicity of X decoders, each connected to a multiplicity of said logic cells, with a multiplicity of word lines;

wherein said word lines select one of a multiplicity of said tristate inverters.