LVDS output driver having low supply voltage capability

• US 7,068,077 B1
• Filed: 03/30/2004
• Issued: 06/27/2006
• Est. Priority Date: 04/17/2003
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Reinschmidt, Robert M.
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US10/815,057
• Time in Patent Office: 819 Days
• Field of Search: 326/32, 326/87, 326/115, 326/121, 326/122, 327/534, 327/535, 327/537, 327/170, 327/172, 327/381, 327/391, 330/253, 330/261, 330/252
• US Class Current: 326/83
• CPC Class Codes: H04L 25/0264 Arrangements for coupling to transmission lines duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission

Abstract

A LVDS output driver has been disclosed. One embodiment of the LVDS output driver includes a number of source followers, each of the source followers including a pull-down transistor having a source, a drain, a gate, and a bulk terminal. The embodiment of the LVDS output driver further includes a number of pull-up transistors, each of the pull-up transistors having a source, a drain, and a gate, wherein the drain of each of the pull-up transistors is coupled to the source of a pull-down transistor of the source followers, to output a number of differential signals via the drains of the pull-up transistors. Other embodiments are described and claimed.

Claims

1. An apparatus, comprising:

a plurality of source followers, each of the plurality of source followers comprising a pull-down transistor having a source, a drain, a gate, and a bulk terminal;

a plurality of pull-up transistors, each of the plurality of pull-up transistors having a source, a drain, and a gate, wherein the drain of each of the plurality of pull-up transistors is coupled to the source of a pull-down transistor of the plurality of source followers, to output a plurality of differential signals via the drains of the plurality of pull-up transistors;

a first current source coupled to the sources of the plurality of pull-up transistors, wherein the first current source is powered by a first voltage of at least about 1.624V to 2.725V;

an operational amplifier, coupled to the first current source, to drive the first current source; and

a feedback path coupled between the drains of the plurality of pull-up transistors and an input of the operational amplifier.

2. An apparatus, comprising:

a plurality of source followers, each of the plurality of source followers comprising a pull-down transistor having a source, a drain, a gate, and a bulk terminal;

a plurality of pull-up transistors, each of the plurality of pull-up transistors m having a source, a drain, and a gate, wherein the drain of each of the plurality of the pull-up transistors is coupled to the source of a pull-down transistor of the plurality of source followers, to output a plurality of differential signals via the drains of the plurality of pull-up transistors;

a first current source coupled to the sources of the plurality of pull-up transistors;

an operational amplifier, coupled to the first current source, to drive the first current source; and

a feedback path coupled between the drains of the plurality of pull-up;

transistors and an input of the operational amplifier, wherein the feedback path further comprises a sensing circuit, the sensing circuit includes a plurality of transistors biased by a predetermined voltage.

3. The apparatus of claim 2, wherein the first current source is powered by a first voltage of at least about 1.624V to 2.725V.

4. An apparatus, comprising:

a plurality of source followers, each of the plurality of source followers comprising a pull-down transistor having a source, a drain, a gate, and a bulk terminal;

a plurality of pull-up transistors, each of the plurality of pull-up transistors CD having a source, a drain, and a gate, wherein the drain of each of the plurality of pull-up transistors is coupled to the source of a pull-down transistor of the plurality of source followers, to output a plurality of differential signals via the drains of the plurality of pull-up transistors;

a low swing differential pre-driver, coupled to the gates of the pull-down m transistors of the plurality of source followers, to drive the pull-down transistors; and

a plurality of inverters, each of the plurality of inverters being coupled to the gate of each of the plurality of pull-up transistors to amplify an input signal and to apply the amplified signal to the gate of the corresponding pull-up transistor, wherein the plurality of inverters are powered by a second voltage approximately between 1.1V and 1.3V.

5. The apparatus of claim 4,

a plurality of source followers, each of the plurality of source followers comprising a pull-down transistor having a source, a drain, a gate, and a bulk terminal;

a plurality of pull-up transistors, each of the plurality of pull-up transistors having a source, a drain, and a gate, wherein the drain of each of the plurality of pull-up transistors is coupled to the source of a pull-down transistor of the plurality of source followers, to output a plurality of differential signals via the drains of the plurality of pull-up transistors; and

a low swing differential pre-driver, coupled to the gates of the pull-down transistors of the plurality of source followers, to drive the pull-down transistors,

wherein the low swing differential pre-driver comprises;

a second current source;

a current sink including a transistor and a resistor, the transistor being coupled to the resistor in parallel; and

a load, coupled between the second current source and the current sink, to output a plurality of low swing differential signals, wherein each of the plurality of low swing differential signals drives the gate of the pull-down transistor of one of the plurality of source followers.

6. The apparatus of claim 5, further comprising a plurality of inverters, each of the plurality of inverters being coupled to the gate of each of the plurality of pull-up transistors to amplify an input signal and to apply the amplified signal to the gate of the corresponding pull-up transistor, wherein the plurality of inverters are powered by a second voltage approximately between 1.1V and 1.3V.

7. The apparatus of claim 4, further comprising:

a network interface including the plurality of pull-up transistors and the plurality of source followers; and

a plurality of transmission lines coupled to the network interface, the plurality of transmission lines being driven by the plurality of low voltage differential signals.

8. The apparatus of claim 7, further comprising a network component coupled to the network interface via the plurality of transmission lines, wherein the network component includes a storage device.

9. A method comprising:

providing a plurality of input signals to a plurality of pull-up transistors;

coupling each of the plurality of pull-up transistors to one of a plurality of pull-down transistors;

driving the plurality of pull-down transistors with a plurality of differential low swing signals to output a plurality of low voltage differential signals in response to the plurality of input signals; and

generating the plurality of differential low swing signals using a low swing differential pre-driver, wherein generating the plurality of differential low swing signals using the low swing differential pre-driver comprises;

supplying current to a load from a second current source;

sinking the current from the load via a transistor and a resistor, the transistor being coupled to the resistor in parallel; and

outputting a plurality of low swing differential signals via the load to the gates of the plurality of pull-down transistors.

10. The method of claim 9, further comprising reducing body effect on the plurality of pull-down transistors.

11. The method of claim 9, further comprising;

supplying current to the plurality of pull-up transistors from a first current source;

sensing one of the plurality of low voltage differential signals to produce a feedback signal; and

driving the first current source with an operational amplifier in response to the feedback signal.

12. A method, comprising

providing a plurality of input signals to a plurality of pull-up transistors,

coupling each of the plurality of pull-up transistors to one of a plurality of pull-down transistors;

driving the plurality of pull-down transistors with a plurality of differential low swing signals to output a plurality of low voltage differential signals in response to the plurality of input signals;

amplifying the plurality of input voltages using a plurality of inverters, each of the plurality of inverters being coupled to a distinct one of the plurality of pull-up transistors; and

powering the plurality of inverters by a voltage approximately between 1.1V and 1.3V.

13. An apparatus comprising:

means for providing a plurality of input signals to a plurality of pull-up transistors;

means for coupling each of the plurality of pull-up transistors to one of a plurality of pull-down transistors;

means for driving the plurality of pull-down transistors with a plurality of differential low swing signals to output a plurality of low voltage differential signals in response to the plurality of input signals;

means for generating the plurality of differential low swing signals using a low swing differential pre-driver, wherein the means for generating the plurality of differential low swing signals using the low swing differential pre-driver comprises;

means for supplying current to a load from a second current source;

means for sinking the current from the load via a transistor and a resistor, the transistor being coupled to the resistor in parallel; and

In

means for outputting a plurality of low swing differential signals via H the load to the gates of the plurality of pull-down transistors.