High-density MOS-decoded unary DAC

• US 7,068,194 B1
• Filed: 03/21/2005
• Issued: 06/27/2006
• Est. Priority Date: 03/21/2005
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Taft, Robert Callaghan
• Primary Examiner(s): Nguyen, John B
• Application Number:
  US11/085,909
• Time in Patent Office: 463 Days
• Field of Search: 341/136, 341/133, 341/144, 341/145, 341/134, 341/135
• US Class Current: 341/136
• CPC Class Codes: H03M 1/0602 of deviations from the desired transfer characteristic H03M1/0617 takes precedence
• CPC Class Codes: H03M 1/747 with equal currents which are switched by unary decoded digital signals

Abstract

Multiple switching circuits and current source circuits are arranged to operate as part of a compact unary DAC cell. The compact unary DAC cell can be combined with additional compact unary DAC cells to provide a scalable unary DAC system that may be segmented, non-segmented, single-ended, differential, or some other DAC topology that may employ one or more unary DAC cells. Each unary DAC cell is preferably comprised of transistors of a single type such that the maximum circuit density can be achieved. The current source circuits may each have equal current magnitudes. The total output current from the unary DAC cell corresponds to the combined currents from each of the current sources that are enabled.

Claims

1. An apparatus for converting a digital input signal to an output current at an output terminal, the apparatus comprising:

a first transistor circuit that is arranged to operate as a first current source that is selectively enabled via a first control terminal, wherein;

the first transistor circuit is comprised of a single transistor type, and a first current from the first transistor circuit is coupled to the output terminal when the first transistor circuit is enabled;

a second transistor circuit that is arranged to operate as a second current source that is selectively enabled via a second control terminal, wherein;

the second transistor circuit is comprised of the single transistor type, a second current from the second transistor circuit is coupled to the output terminal when the second transistor circuit is enabled, and a magnitude associated with the first current is substantially matched to a magnitude associated with the second current;

a first switching circuit that is arranged to selectively couple a first input terminal to the first control terminal in response to a first control signal, wherein the first switching circuit is comprised of the single transistor type;

a second switching circuit that is arranged to selectively couple a second input terminal to the first control terminal in response to a second control signal that is an inverse of the first control signal, wherein the second switching circuit is comprised of the single transistor type; and

a third switching circuit that is arranged to selectively couple the first input terminal to the second input terminal in response to a third control signal, wherein;

the second input terminal is coupled to the second control terminal, and the third switching circuit is comprised of the single transistor type.

2. The apparatus of claim 1, further comprising a buffer logic circuit that is arranged to provide the first, second, and third control signals in response to the digital input signal.

3. The apparatus of claim 1, wherein the single transistor type corresponds to one of:

an n-type transistor, a p-type transistor, an NMOS type transistor, and a PMOS type transistor.

4. The apparatus of claim 1, wherein each of the transistor circuits comprises at least one of:

a first current source type that is biased by a bias signal that is provided from the corresponding control terminal, a second current source type that includes a series switching transistor that is selectively enabled by a control signal that is provided to the corresponding control terminal, a third current source type that includes a series coupled transistor that is selectively biased by a cascode bias signal that is provided from the corresponding control terminal, and a fourth current source type that includes a series coupled transistor that is selectively biased by a power signal that is provided from the corresponding control terminal.

5. The apparatus of claim 1, further comprising:

a third transistor circuit that is arranged to operate as a third current source that is selectively enabled via a third control terminal, wherein;

the third transistor circuit is comprised of the single transistor type, a third current from the third transistor circuit is coupled to the output terminal when the third transistor circuit is enabled, a magnitude associated with the third current is substantially matched to a magnitude associated with the first current, and the third control terminal is coupled to the first input terminal.

6. The apparatus of claim 1, wherein the output current corresponds to at least one of:

a single output current from a unary DAC, a differential output current from a unary DAC, a single output current from a segmented unary DAC, and a differential output current from a segmented unary DAC.

7. The apparatus of claim 1, further comprising:

a third transistor circuit that is arranged to operate as a third current source that is selectively enabled via a third control terminal, wherein;

the third transistor circuit is comprised of the single transistor type, a third current from the third transistor circuit is coupled to the output terminal when the third transistor circuit is enabled, and a magnitude associated with the third current is substantially matched to the magnitude of the first current;

a fourth transistor circuit that is arranged to operate as a fourth current source that is selectively enabled via a fourth control terminal, wherein;

the fourth transistor circuit is comprised of the single transistor type, a fourth current from the fourth transistor circuit is coupled to the output terminal when the second transistor circuit is enabled, and a magnitude associated with the fourth current is substantially matched to the magnitude associated with the first current;

a fourth switching circuit that is arranged to selectively couple the second input terminal to the third control terminal in response to the first control signal, wherein the fourth switching circuit is comprised of the single transistor type;

a fifth switching circuit that is arranged to selectively couple a third input terminal to the third control terminal in response to the second control signal, wherein the fifth switching circuit is comprised of the single transistor type; and

a sixth switching circuit that is arranged to selectively couple the second input terminal to the third input terminal in response to a fourth control signal that is an inverse of the third control signal, wherein;

the third input terminal is coupled to the fourth control terminal, and the sixth switching circuit is comprised of the single transistor type.

8. The apparatus of claim 7, further comprising a seventh switching circuit that is arranged to selectively couple the first input terminal to the third input terminal in response to a fifth control signal.

9. An apparatus for converting a digital input signal to an output current at an output terminal, comprising:

a first unary DAC cell that includes a first input terminal, a second input terminal, and a first control terminal, wherein the first unary DAC cell is arranged to provide a first current in response to a control signal that is received at the first control terminal;

a second unary DAC cell that includes a third input terminal, a fourth input terminal, and a second control terminal, wherein the second unary DAC cell is arranged to provide a second current in response to the control signal that is received at the second control terminal;

a third unary DAC cell that includes a fifth input terminal, a sixth input terminal, and a third control terminal, wherein the third unary DAC cell is arranged to provide a third current in response to the control signal that is received at the third control terminal;

a fourth unary DAC cell that includes a seventh input terminal, an eighth input terminal, and a fourth control terminal, wherein the third unary DAC cell is arranged to provide a fourth current in response to the control signal that is received at the fourth control terminal, and wherein the first, second, third, and fourth currents are combined to provide at least a portion of the output current at the output terminal;

a first input signal that is coupled to the first input terminal;

a second input signal that is coupled to the eighth input terminal;

a first switching circuit that is arranged to selectively couple the first input signal to the second and third input terminals in response to a second control signal;

a second switching circuit that is arranged to selectively couple the second and third input terminals to the fourth and fifth input terminals in response to an inverse of the second control signal;

a third switching circuit that is arranged to selectively couple the fourth and fifth input terminals to the sixth and seventh input terminals in response to the second control signal;

a fourth switching circuit that is arranged to selectively couple the sixth and seventh input terminals to the eighth input terminal in response to the inverse of the second control signal;

a fifth switching circuit that is arranged to selectively couple the first input signal to the fourth and fifth input terminals in response to a third control signal;

a sixth switching circuit that is arranged to selectively couple the second input signal to the fourth and fifth input terminals in response to an inverse of the third control signal.

10. The apparatus of claim 9, wherein the first control signal corresponds to one of:

a set of control signals, a setoff inverse control signals, and a set of control signals and their corresponding inverses.

11. The apparatus of claim 9, wherein the first, second, third, fourth, fifth and sixth switching circuit each correspond to a transistor circuit that is arranged with transistors of a single type.

12. The apparatus of claim 9, wherein the first, second, third, and fourth unary DAC cells each comprise one of:

a 2-bit unary DAC cell, a 3-bit unary DAC cell, a 4-bit unary DAC cell, a 5-bit unary DAC cell, and an N-bit unary DAC cell.

13. The apparatus of claim 9, wherein the first, second, third, and fourth unary DAC cells are matched to one another, each of the unary DAC cells comprising:

a first transistor circuit that is arranged to operate as a first current source that is selectively enabled via a first control port, wherein;

the first transistor circuit is comprised of a single transistor type;

a second transistor circuit that is arranged to operate as a second current source that is selectively enabled via a second control port, wherein a magnitude associated with the first current is substantially matched to a magnitude associated with the second current;

a first switch circuit that is arranged to selectively couple an input terminal of the unary DAC cell to the first control port in response to a first unary DAC control signal; and

a second switch circuit that is arranged to selectively couple a second input terminal of the unary DAC cell to the first control port in response to a second unary DAC control signal that is an inverse of the first unary DAC control signal.

14. The apparatus of claim 13, wherein the first transistor circuit, second transistor circuit, first switch circuit, and second switch circuit are comprised of transistors of a single type.

15. The apparatus of claim 9, wherein the first, second, third, and fourth unary DAC cells are matched to one another, each of the unary DAC cells comprising:

a first transistor circuit that is arranged to operate as a first current source that is selectively enabled via a first control port, wherein;

the first transistor circuit is comprised of a single transistor type;

a second transistor circuit that is arranged to operate as a second current source that is selectively enabled via a second control port, wherein the second transistor circuit is comprised of the single transistor type;

a third transistor circuit that is arranged to operate as a third current source that is selectively enabled via a third control port, wherein;

the third transistor circuit is comprised of the single transistor type, and a magnitude associated with the first, second, and third currents are substantially matched to one another;

a first switch circuit that is arranged to selectively couple an input port of the unary DAC cell to the first control port in response to a first unary DAC control signal;

a second switch circuit that is arranged to selectively couple the first control port to the second control port in response to a first inverse unary DAC control signal;

a third switch circuit that is arranged to selectively couple the second control port to the third control port in response to the first unary DAC control signal;

a fourth switch circuit that is arranged to selectively couple a second input port of the unary DAC cell to the third control port in response to the first inverse unary DAC control signal;

a fifth switch circuit that is arranged to couple the first input port of the unary DAC cell to the second control port in response to a second unary DAC control signal; and

a sixth switch circuit that is arranged to couple the second input port of the unary DAC cell to the second control port in response to an inverse of the second unary DAC control signal.

16. The apparatus of claim 13, wherein the first transistor circuit, second transistor circuit, third transistor circuit, first switch circuit, second switch circuit, third switch circuit, fourth switch circuit, and fifth switch circuit are comprised of transistors of a single type.

17. An apparatus for converting a digital input signal to an output current at an output terminal, comprising:

a first current source means that includes a first control terminal, wherein the first current source means is arranged to provide a first current when enabled via the first control terminal;

a second current source means that includes a second control terminal, wherein the second current source means is arranged to provide a second current when enabled via the second control terminal;

a third current source means that includes a third control terminal, wherein the third current source means is arranged to provide a third current when enabled via the third control terminal;

a means for combining the first, second, and third currents to provide at least a portion of the output current;

a first switching means that is arranged to selectively couple a first input terminal to the first control terminal in response to a first control signal;

a second switching means that is arranged to selectively couple the first control terminal to the second control terminal in response to an inverse of the first control signal;

a third switching means that is arranged to selectively couple the second control terminal to the third control terminal in response to the first control signal;

a fourth switching means that is arranged to selectively couple a second input terminal to the third control terminal in response to the inverse of the first control signal;

a fifth switching means that is arranged to selectively couple the first input terminal to the second control terminal in response to a second control signal; and

a sixth switching means that is arranged to selectively couple the second input terminal to the second control terminal in response to an inverse of the second control signal.

18. The apparatus of claim 17, wherein the first current source means, second current source means, third current source means, first switching means, second switching means, third switching means, fourth switching means, fifth switching means, and sixth switching means are comprised of transistors of a single type.

19. The apparatus of claim 17, wherein the first, second, and third currents have substantially the same magnitude.

20. The apparatus of claim 17, wherein the output current corresponds to one of two output currents that are associated with a differential output current.