CMOS image sensor with a low-power architecture
First Claim
Patent Images
1. An image sensor, comprising:
- an array of photosensing devices arranged into columns and rows;
a column readout part which reads out charges captured by said photosensing devices a row at a time;
a gain stage, coupled to receive an output of said column readout part, and to increase a signal level of said readout part output; and
an output driving stage, which drives an output signal,wherein each of said column readout part, said gain stage, and said output driving stage include at least one element which optimizes a power consumption of the stage independent of other stages.
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Abstract
A system of reducing power consumption in and active pixels sensor. The sensor is broken into different blocks, and each of the blocks is individually optimized. The optimization may include minimizing the parasitic capacitance on the readout bus, turning off biases when not in use, and operating in a way that minimizes static power consumption of different elements such as A/D converters.
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Citations
24 Claims
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1. An image sensor, comprising:
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an array of photosensing devices arranged into columns and rows; a column readout part which reads out charges captured by said photosensing devices a row at a time; a gain stage, coupled to receive an output of said column readout part, and to increase a signal level of said readout part output; and an output driving stage, which drives an output signal, wherein each of said column readout part, said gain stage, and said output driving stage include at least one element which optimizes a power consumption of the stage independent of other stages. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An image sensor, comprising:
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an array of photosensitive pixels producing output signals indicative of values of said pixels; and first and second A/D converters, said first A/D converter associated with first color pixels, and said second A/D converter associated with second color pixels, said first and second A/D converters having staggered operating timing, such that one of the A/D converters starts operating when a different A/D converter is continuing to operate, wherein said first A/D converter receives data from green pixels, and said second A/D converter receives data from red and blue pixels and wherein said A/D converters are successive approximation A/D converters.
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17. An image sensor, comprising:
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an array of photosensitive pixels; and timing and control logic, having a plurality of control parts, said plurality of control parts individually controllable and turned off when not in use, wherein said control part includes a controllable bias element which is turned off to remove said bias when not in use, and wherein one of said plurality of control parts is a voltage clamp which is turned off when not in use. - View Dependent Claims (18)
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19. An image sensor, comprising:
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an array of photosensitive pixels; timing and control logic, having a plurality of control parts, said plurality of control parts individually controllable and turned off when not in use; and an element that minimizes parasitic capacitance on the readout bus, wherein said element includes an optimized gain element with first and second unity buffer stages, and a gain stage, said first and second buffer stages isolating a gain stage from the readout bus.
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20. An image sensor, comprising:
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an array of photosensitive pixels; and timing and control logic, having a plurality of control parts, said plurality of control parts individually controllable and turned off when not in use, wherein said timing and control logic produces a converter reference voltage, a clamped voltage, and a common mode feedback voltage, and where each of said converter reference voltage, clamped voltage, and common mode feedback voltage are produced by separate, controllable sources, which are turned off when not in use.
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21. A method, comprising:
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reading out pixel values from an array of photosensitive pixels; A/D converting pixel values from green pixels in a first A/D converter, at a first timing and A/D converting pixel values from blue pixels in a second A/D converter at a second timing offset from said first;
timing,wherein said second timing is 50 percent of the way through a conversion cycle represented by said first timing.
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22. A method, comprising:
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reading out pixel values from an array of photosensitive pixels; A/D converting pixel values from green pixels in a first A/D converter, at a first timing; and A/D converting pixel values from blue pixels in a second A/D converter at a second timing offset from said first timing, wherein said A/D converting comprises successive approximation A/D converting.
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23. A method of acquiring an image, comprising:
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producing bias electrical values to be used as part of acquiring image signals; and turning off said bias electrical signals at times during the acquiring when the biases are not needed, wherein the bias signals include a clamped signal. - View Dependent Claims (24)
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Specification