Nonvolatile memory and method of erasing for nonvolatile memory

• US 7,068,541 B2
• Filed: 11/05/2003
• Issued: 06/27/2006
• Est. Priority Date: 11/20/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Sakamoto, Yoshinori, Bando, Tatsuya
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/700,592
• Publication Number:
  US 20040095809A1
• Time in Patent Office: 965 Days
• Field of Search: 365/185.27, 365/185.29
• US Class Current: 365/185.27
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing

Abstract

The number of rewrites for memory cells is to be increased, and the reliability of data reading to be substantially improved. Where data in memory cells are to be erased, the switching of an erase voltage to be applied to the control gate of each memory cell, while switching from one to another of voltages of any different levels, as the control gate voltage (=soft erase voltage) is accomplished according to the quantity of electric charges accumulated at the floating gate of each memory cell so as to keep substantially constant the voltage applied to the tunnel film of the memory cell. Upon acceptance of an erase command, a CPU supplies a control signal to a decoder, and on the basis of the resultant decode signal an erase voltage switching circuit generates a soft erase voltage of a certain level. After that, while switching from one to another of soft erase voltages differing in level, data in the memory cell are erased. Upon completion of erasing data in the memory cell, erase verification is carried out.

Claims

1. A nonvolatile memory comprising:

a memory array unit having a plurality of nonvolatile memory cells;

a control unit; and

a voltage generating unit for supplying voltages to said nonvolatile memory cells,

wherein said nonvolatile memory cells store information corresponding to a quantity of electric charges in a floating gate of each nonvolatile memory cell,

wherein said control unit controls a write operation to store information into said nonvolatile memory cells, a read operation to read information stored in said nonvolatile memory cells; and

an erase operation to erase information stored in said nonvolatile memory cells,

wherein said voltage generating unit has an erase voltage generating unit for generating, in accordance with control from said control unit, erase voltages to be applied to said nonvolatile memory cells in said erase operation, and

wherein said erase voltage generating unit generates, in response to a control signal supplied from said control unit, erase voltages of two or more levels including a lower erase voltage and a higher erase voltage, and

wherein said control unit performs control such that in said erase operation the lower erase voltage is applied to a control gate of each of said nonvolatile memory cells and thereafter the higher erase voltage is applied to the control gate of each of said nonvolatile memory cells.

2. The nonvolatile memory according to claim 1, wherein said control unit performs control to verify whether information stored in said nonvolatile memory cells is erased after said higher erase voltage has been applied to the control gates of said nonvolatile memory cells.

3. The nonvolatile memory according to claim 2, wherein the level of said lower erase voltage is lower than the levels of other erase voltages generated by said voltage generating unit.

4. A nonvolatile memory comprising:

a memory array unit having a plurality of nonvolatile memory cells;

a control unit; and

a voltage generating unit for supplying voltages to said nonvolatile memory cells,

wherein said nonvolatile memory cells store information corresponding to a quantity of electric charges in a floating gate of each nonvolatile memory cell,

wherein said control unit controls a write operation to store information into said nonvolatile memory cells, a read operation to read information stored in said nonvolatile memory cells; and

an erase operation to erase information stored in said nonvolatile memory cells,

wherein said voltage generating unit has an erase voltage generating unit for generating, in accordance with control from said control unit, erase voltages to be applied to said nonvolatile memory cells in said erase operation, and

wherein said erase voltage generating unit generates, in response to a control signal supplied from said control unit, erase voltages of two or more levels to make voltages applied to tunnel films of said nonvolatile memory cells substantially constant and applies the erase voltages selectively to a control gate of each of said nonvolatile memory cells.

5. The nonvolatile memory according to claim 4, wherein said control unit perform control to verify whether information stored in said nonvolatile memory cells is erased after a plurality of the erase voltages have been applied to the control gate of each of said nonvolatile memory cells.

6. The nonvolatile memory according to claim 5, wherein, out of the erase voltages generated by said erase voltage generating unit, a first voltage level of an erase voltage first applied to said control gate of any of said nonvolatile memory cell is the lowest, and each of the erase voltages applied second and afterwards is higher in level than the erase voltage applied immediately before.

7. A nonvolatile memory comprising, on one semiconductor substrate:

a memory array unit;

a control unit; and

a voltage generating unit,

wherein said memory array unit has a plurality of word lines and a plurality of nonvolatile memory cells,

wherein each said nonvolatile memory cells includes a first terminal connected to a first semiconductor region, a second terminal connected to a second semiconductor region, and a third terminal connected to a control gate,

wherein a channel region is disposed between said first semiconductor region and said second semiconductor region, an electric charge accumulating region is disposed between the control gate and the channel region, a first insulating film is disposed between the electric charge accumulating region and the channel region,

wherein the third terminal of at least one said nonvolatile memory cell is connected to each word line,

wherein data are stored into each nonvolatile memory cell according to a quantity of electric charges accumulated in said electric charge accumulating region; and

the quantity of electric charges is controlled by said control unit performing a first operation to inject electric charges into said electric charge accumulating region and a second operation to eject electric charges from said electric charge accumulating region,

wherein, in order to perform said second operation, a first voltage generated by said voltage generating unit is applied between said control gate and said channel region via a word line connected to the control gate, and

wherein, during a period of said second operation, said first voltage generated by said voltage generating unit is varied two or more times, so as to keep voltage applied to said first insulating film within a first voltage range.

8. The nonvolatile memory according to claim 7,

wherein, during said first operation, a second voltage generated by said voltage generating unit is applied between said control gate and said channel region via the word line connected to the control gate, and

wherein, during said first operation, said second voltage generated by said voltage generating unit is varied.

9. The nonvolatile memory according to claim 8, wherein said first voltage applied between said control gate and said channel region in said first operation differs in polarity from said second voltage applied between said control gate and said channel region in said second operation.

10. The nonvolatile memory according to claim 9,

wherein the threshold voltage of each nonvolatile memory cell is varied according to the quantity of electric charges accumulated in said electric charge accumulating region so as to be included in a plurality of threshold voltage distributions according to data to be stored into said nonvolatile memory cell,

wherein in said first operation, the threshold voltage of at least one said nonvolatile memory cell connected to one word line is moved into a first threshold voltage distribution, and a first determination is made during said first operation as to whether the threshold voltage of said at least one nonvolatile memory cell is moved within said first threshold voltage distribution, and

wherein in said second operation, the threshold voltages of all of the nonvolatile memory cells connected to said one word line are moved into a second threshold voltage distribution, and a second determination is made during said second operation as to whether the threshold voltages of those nonvolatile memory cells are moved within said second threshold voltage distribution.