Dual use block/stream cipher

• US 7,068,786 B1
• Filed: 08/29/1999
• Issued: 06/27/2006
• Est. Priority Date: 08/29/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Graunke, Gary L., Lee, David A., Faber, Robert W.
• Primary Examiner(s): Barron, Jr., Gilberto
• Assistant Examiner(s): Kim, Jung W.
• Application Number:
  US09/385,591
• Time in Patent Office: 2,494 Days
• Field of Search: 380/29, 380/37, 380/44, 780/250, 708/250
• US Class Current: 380/44
• CPC Class Codes: H04L 2209/34 Encoding or coding, e.g. Huffman coding or error correction
• CPC Class Codes: H04L 9/0618 Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
• CPC Class Codes: H04L 9/065 Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3

Abstract

A dual use block/stream cipher is provided with a first key section and a data section. The first key section is to be initialized with a first cipher key, and to successively transform the first cipher key or a modified version of the first cipher key. The data section, coupled to the first key section, is to be initialized with either a block of plain text or a random number, and to successively and dependently, on the first key section, transform the plain text/random number. The cipher is further provided with a second key section and a mapping function. The second key section, coupled to the first key section, is selectively enableable to modify the first cipher key. The mapping section, coupled to the first key section, is to generate a pseudo random bit sequence when the second key section is selectably enabled to modify the stored first cipher key.

Claims

1. An encoding apparatus comprising:

a block cipher key section to be initialized with a block cipher key, having transformation units to transform the block cipher key into a transformed block cipher key;

a data section coupled with the block cipher key section to be initialized with a random number, having transformation units to transform the random number based on the transformed block cipher key;

a stream cipher key section coupled with the block cipher key section to modify the block cipher key according to a stream cipher key to produce data bits to dynamically modify the random number into a modified random number in the data block section, wherein the stream cipher key section further includes linear feedback shift registers (LFSRs) to generate a first, second, and third sequence of data bits, and a serial network of shuffle units to shuffle the third sequence of data bits using the first sequence of data bits and input bits and the second sequence of data bits and control bits to the serial network of shuffle units; and

a mapping section to receive the modified random number and the transformed block cipher key and generate a pseudo random bit sequence based on the modified random number and the transformed block cipher key.

2. An apparatus according to claim 1, wherein the block cipher key section further includes first, second, and third registers, to be collectively initialized with the block cipher key.

3. An apparatus according to claim 2, wherein the block cipher key section further includes substitution units coupled between an output of the first register and an input of the third register, to make at least a partial substitution to the content of the first register and store the substituted content in the third register.

4. An apparatus according to claim 2, wherein the block cipher key section further includes a linear transformation unit coupled between an output of the second register and an input of the first register and an output of the third register and an input of the second register, to produce a linearly transformed version of the content of the second and third registers, and store the linearly transformed versions in the first and second registers, respectively.

5. An apparatus according to claim 1, wherein the data section is initialized with plain text.

6. An apparatus according to claim 1, wherein the data section is initialized with derived random number Mi-1.

7. An apparatus according to claim 1, wherein the data section further includes fourth, fifth, and sixth registers, to be collectively initialized with the random number.

8. An apparatus according to claim 7, wherein the data section further includes substitution units coupled between an output of the fourth register and an input of the sixth register, to make at least a partial substitution to the content of the fourth register and store the substituted content in the sixth register.

9. An apparatus according to claim 7, wherein the data section further includes a linear transformation unit coupled between an output of the fifth register and an input of the fourth register and an output of the sixth register and an input of the fifth register, to produce a linearly transformed version of the content of the fifth and sixth registers, and store the linearly transformed versions in the fourth and fifth registers, respectively.

10. An apparatus according to claim 7, wherein the block cipher key section includes first, second, and third registers to be collectively initialized with the block cipher key, and wherein the mapping section comprises a plurality of logical gates coupled with a register in the block cipher key section and a register in the data section.

11. An apparatus comprising:

a first key section to be enabled in a stream cipher mode and disabled in a block cipher mode, and to selectively modify a cipher key into a selectively modified cipher key;

a second key section to be coupled with the first key section in the stream cipher mode, and having a first, second, and third registers to be collectively initialized with the cipher key, and transformation units coupled with the first, second, and third registers to recursively transform the selectively modified cipher key into a transformed selectively modified cipher key;

a data section coupled with the second key section, having a fourth, fifth, and sixth registers to be collectively initialized with a data bit sequence, and transformation units coupled with the fourth, fifth, and sixth registers to transform the data bit sequence into a transformed data bit sequence according to the transformed selectively modified cipher key; and

a mapping section coupled with the second key section and the data section to generate a pseudo random bit sequence with the transformed data bit sequence.

12. An apparatus according to claim 11, wherein the first key section further includes linear feedback shift registers (LFSRs) to generate a first, second, and third sequence of data bits, and a serial network of shuffle units to shuffle the third sequence of data bits using the first sequence of data bits and input bits and the second sequence of data bits and control bits to the serial network of shuffle units.

13. An apparatus according to claim 11, wherein the second key section further includes substitution units coupled between an output of the first register and an input of the third register, to make at least a partial substitution to the content of the first register and store the substituted content in the third register.

14. An apparatus according to claim 11, wherein the second key section further includes a linear transformation unit coupled between an output of the second register and an input of the first register and an output of the third register and an input of the second register, to produce a linearly transformed version of the content of the second and third registers, and store the linearly transformed versions in the first and second registers, respectively.

15. An apparatus according to claim 11, wherein the data section is initialized with plain text.

16. An apparatus according to claim 11, wherein the data section is initialized with derived random number Mi-1.

17. An apparatus according to claim 11, wherein the data section further includes substitution units coupled between an output of the fourth register and an input of the sixth register, to make at least a partial substitution to the content of the fourth register and store the substituted content in the sixth register.

18. An apparatus according to claim 11, wherein the data section further includes a linear transformation unit coupled between an output of the fifth register and an input of the fourth register and an output of the sixth register and an input of the fifth register, to produce a linearly transformed version of the content of the fifth and sixth registers, and store the linearly transformed versions in the fourth and fifth registers, respectively.

19. An apparatus according to claim 11, wherein the mapping section comprises a plurality of logical gates coupled with a register in the second key section and a register in the data section.