Method and system for performance level modeling and simulation of electronic systems having both hardware and software elements

• US 7,069,204 B1
• Filed: 09/28/2000
• Issued: 06/27/2006
• Est. Priority Date: 09/28/2000
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Lavagno, Luciano, O'Brien-Strain, Eamonn, Chao, Qizhang, Harcourt, Edwin A., Hoover, Christopher, Bhatnagar, Neeti K., La Rue, William W. Jr., Dunlop, Douglas D., Beverly, Aaron, Solden, Sherry, Chakravarty, Sanjay, Desai, Soumya, Chiodo, Massimiliano L., Agrawal, Poonam, Sholes, Michael D., Chou, Hungming
• Primary Examiner(s): Rodriguez, Paul L.
• Assistant Examiner(s): Craig, Dwin M.
• Application Number:
  US09/670,911
• Time in Patent Office: 2,098 Days
• Field of Search: 703/14, 716/7
• US Class Current: 703/14
• CPC Class Codes: G06F 11/3447 Performance evaluation by modeling
• CPC Class Codes: G06F 11/3457 Performance evaluation by simulation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method and system for evaluating performance level models of electronic systems having both hardware and software components is provided. The system and method allow for the simplified implementation and testing of several different architectural designs for compliance with the desired operational requirement of a designed electronic system.

Claims

1. A computer implemented method of modeling an electronic system having both hardware and software elements, comprising,

capturing a plurality of behaviors that correspond to operations performed by the system being modeled;

capturing a plurality of hardware and software architectural components the plurality being contained within an architectural platform;

mapping each of the captured behaviors of the plurality of behaviors to a selected architectural component to perform the behavior;

recognizing and capturing communication patterns among the architectural components that require communication among them in order to perform the behaviors; and

mapping each instance of communication between behaviors to an instance of the captured pattern;

wherein;

the architectural components include software and hardware architectural blocks; and

the method further comprising the steps of,

re-mapping portions of the behavioral blocks to different architectural blocks and causing implementations of behavior to move between hardware and software.

2. The method according to claim 1, wherein the step of re-mapping comprises iteratively re-mapping until the modeled system meets specific performance requirements.

3. The method according to claim 1, wherein said step of re-mapping is performed to alter the communications patterns.

4. The method of claim 1 wherein each architectural component comprises a plurality of services each service corresponding to a particular function of the architectural component.

5. The method of claim 4 wherein each service comprises a declaration and a definition corresponding to the interface and body of the service, respectively.

6. The method of claim 5 wherein each service definition uses other services.

7. The method of claim 1 further comprising a step of partitioning each behavior of the plurality of behaviors that are captured as either a hardware or software behavior.

8. The method of claim 1 further comprising modifying the plurality of architecture components that are contained in an architecture while maintaining previously captured behavior mappings and communication patterns.

9. The method of claim 1 further comprising simulating operation of the electronic system when performing the plurality of behaviors utilizing the architecture services of the mapped behaviors and optionally the pattern services that were selected.

10. The method of claim 9 wherein utilizing the architecture services can be successively refined where additional design decisions are made causing the performance model to become more accurate.

11. A computer implemented method of modeling an electronic system having both hardware and software elements, comprising:

capturing a plurality of behaviors that correspond to operations performed by the system being modeled;

capturing a plurality of hardware and software architectural components the plurality being contained within an architectural platform;

mapping each of the captured behaviors of the plurality of behaviors to a selected architectural component to perform the behavior;

recognizing and capturing communication patterns among the architectural components that require communication among them in order to perform the behaviors; and

mapping each instance of communication between behaviors to an instance of the captured pattern;

wherein the architectural components are high level architectural components and not component level design items.

12. The method according to claim 11, wherein at least on the high level architectural components is one of a series of Real Time Operating System (RTOS) scheduling components.

13. The method of claim 11 further comprising at least one member of a group consisting of reuse of services in other architecture components and reuse of architecture components in other architecture platforms or reuse of architecture platforms in other electronic systems.

14. The method of claim 11 wherein said capturing communication pattern step comprises a plurality of services each service uses other service declarations that are supported by the architecture component to which the behavior is mapped.

15. A computer implemented method of modeling an electronic system having both hardware and software elements, comprising:

capturing a plurality of behaviors that correspond to operations performed by the system being modeled;

capturing a plurality of hardware and software architectural components the plurality being contained within an architectural platform;

mapping each of the captured behaviors of the plurality of behaviors to a selected architectural component to perform the behavior;

recognizing and capturing communication patterns among the architectural components that require communication among them in order to perform the behaviors; and

mapping each instance of communication between behaviors to an instance of the captured pattern

wherein the communication patterns include each of timing, speed and protocols that are required to carry out communication between the separate architectural components.

16. The method of claim 15 wherein the step of capturing the architectural platform comprises selecting a performance model for each of the plurality of architectural components wherein the services of one architectural component uses other services that are topologically connected in the platform.

17. The method of claim 15 further comprising associating at least one behavior of the plurality of behaviors with a new architectural component and recognizing and capturing one or more new communication patterns while maintaining other previously captured communication patterns.

18. The method of claim 15 further comprising modifying at least one architecture component of the plurality of architecture components in the platform while maintaining associations amongst the other architecture components and patterns of communication to and from the modified component, this modification can be exchange of component for another component or a tweak to the parameter settings or a different selection of performance model.

19. A computer implemented method, of modeling an electronic system having both hardware and software elements, comprising:

capturing a plurality of behaviors that correspond to operations performed by the system being modeled;

capturing a plurality of hardware and software architectural components the plurality being contained within an architectural platform;

mapping each of the captured behaviors of the plurality of behaviors to a selected architectural component to perform the behavior;

recognizing and capturing communication patterns among the architectural components that require communication among them in order to perform the behaviors; and

mapping each instance of communication between behaviors to an instance of the captured pattern;

wherein the step of mapping each instance of communication comprises mapping each instance of communication to a semaphore pattern that includes a sender and receiver pair of pattern services representing each end of the communication.

20. The method of claim 19 further comprising modifying at least one behavior of the plurality of behaviors or associating at least one behavior with a new appropriate architectural component while maintaining associations among the other behaviors with previously mapped architectural components.

21. The method of claim 19 further comprising changing the selection of one or more pattern mappings while maintaining other previously captured communication patterns.

22. The method of claim 19 further comprising reuse of patterns in other electronic systems with variations on the architecture platform.

23. The method according to claim 19, wherein the sender pattern service models locking of a mutex, writing data, unlocking the mutex, and sending a trigger.

24. The method according to claim 23, wherein the receiver pattern service models locking the mutex, reading the data, and unlocking the mutex.

25. The method according to claim 19, further comprising the step of:

selecting a group of patterns from a plurality of pattern groups based on an implementation chosen for the sender receiver pair;

selecting a pattern service to be mapped to each instance of communication from the selected group of patterns;

wherein the plurality of pattern groups include pattern groups for each of ASICs, inter-task software, intra-task software, event trigger transmitting.

26. The method according to claim 25, wherein the patterns in each groups comprise:

HW-HW (a) Direct Connect, (b) Register Mapped, (c) Shared Memory HW-HW Trigger (a) Direct Connect, (b) Register Mapped HW-SW Interrupt Register Mapped, (b) Interrupt Shared Memory, (c) Polling Register Mapped, (d) Polling Shared Memory HW-SW Trigger (a) Interrupt, (b) Polling Register Mapped, (c) Polling Shared Memory SW-HW (a) Register Mapped, (b) Shared Memory SW-HW Trigger (a) Register Mapped SW-SW Inter-task (a) Unprotected, (b) Semaphore Protected, (c) Uninterruptable Protected SW-SW Inter-task (a) Unprotected Trigger SW-SW Intra-task (a) Unprotected SW-SW Intra-task (a) Unprotected Trigger SW->

Memory (a) SWDirectMemoryAccess (b) SWDMAAccess HW->

Memory (a) HWDirectMemoryAccess (b) HWDMAAccess SW->

Timer (a) SWVirtualTimer HW->

Timer (a) ASICInternalTimer

.

27. The method according to claim 26, further comprising the step of:

categorizing each of the communications into one of the groups based on mappings of the behavior components and size of data to be communicated.

28. A system for creating a behavioral model of an electronic system having hardware and software components, comprising:

a plurality of architectural components, each of the architectural components corresponding to a component capable of being implemented as part of the electronic system; and

means for generating communication patterns between the architectural components that require communication between them in order to perform user specified behaviors;

each communication pattern including communication between any intervening architectural components needed to communicate between architectural components carrying out the behaviors;

wherein the architectural components are high level architectural components and not component level design items, wherein the behavioral model is created.

29. A performance level computer implement model of the communications between behaviors of an electronic system having hardware and software components, the model comprising:

an application programming interface for a first behavior that provides data to be transferred to one or more destination behaviors;

a first service that implements the application programming interface that models the performance of the communication protocol, the first service being among a plurality of services supported by the pattern to which the behavior communication is mapped;

one or more application programming interfaces used by the first service to model performance of the architecture platform, the application interfaces being among a plurality of service declarations supported by the symbol of the architectural component to which the first behavior is mapped;

a supported service declaration on the symbol of the architecture component by a service definition, the service definition being among a plurality of service definitions specified by the performance model of the architecture component;

a second application interface that represents a function to be performed by a second architectural component topologically connected to the first component of the electronic system, the second service being one a plurality of second services each corresponding to a function capable of being performed by the second architectural component;

an input application interface on the destination behavior that receives output information of the performance level computer implemented model of the electronic system, thereby completing a communication from source behavior to destination behavior,

wherein the model is configured to,

capture a plurality of behaviors that correspond to operations performed by the system being modeled,

capture a plurality of hardware and software architectural components the plurality being contained within an architectural platform,

map each of the captured behaviors of the plurality of behaviors to a selected architectural component to perform the behavior,

recognize and capture communication patterns among the architectural components that require communication among them in order to perform the behaviors, and

map each instance of communication between behaviors to an instance of the captured pattern and re-map portions of the behavioral blocks to different architectural blocks and causing implementations of behavior to move between hardware and software.