Double data rate synchronous SRAM with 100% bus utilization
First Claim
1. A synchronous memory circuit comprising:
- an address bus for receiving an address;
at least two memory blocks each of which is capable to be accessed at said address; and
a data bus for receiving data items for transfer to or from the memory blocks, wherein in two consecutive clock cycles at least a first and a second write data items corresponding to a first write burst operation are capable of being transferred sequentially to the memory circuit via the data bus and at least a first and second read data items corresponding to a first read burst operation are capable of being provided sequentially by the memory circuit via the data bus, and wherein the data bus is capable of receiving data corresponding to the write burst operation and providing data corresponding to the read burst operation with no dead cycles therebetween; and
further including an output circuit for receiving the at least first and second read data items from respective at least two memory blocks in the first read burst operation and allowing the first read data item to be provided on the data bus half a clock cycle after the first read burst operation is initiated, and allowing the second read data item to be provided on the data bus one clock cycle after the first read burst operation is initiated; and
at least two registers for providing both a burst address received at the address bus and at least one read/write control signal received at least one input terminal of the memory circuit to the at least two memory blocks sequentially in one clock cycle.
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Accused Products
Abstract
A synchronous memory circuit is capable of double data transfer rate per clock cycle, 100% bus utilization (i.e., no idle clock cycles in bus turn arounds), and has only one clock cycle of latency in each of read and write burst operations. The memory circuit has a data bus 202, at least two memory blocks (20, 30), a multiplexer (120) for receiving two read data items from respective two memory blocks in a read burst operation and allowing one of the two read data items to be provided on the data bus half a clock cycle after the read burst operation is initiated and allowing the other one of the two read data items to be provided on the data bus one clock cycle after the read burst operation is initiated, and two registers (50, 70) for storing respective two write data items provided on the data bus in a first write burst operation wherein one of the two write data items is written to one of the two memory blocks at the initiation of a next write burst operation following the first write burst operation and the other one of the two write data items is written to the other one of the two memory blocks half a clock cycle after the initiation of the next write burst operation, wherein in two consecutive clock cycles the two write data items are capable of being transferred to the memory circuit via the data bus and the two read data items are capable of being transferred from the memory circuit via the data bus.
186 Citations
52 Claims
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1. A synchronous memory circuit comprising:
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an address bus for receiving an address;
at least two memory blocks each of which is capable to be accessed at said address; and
a data bus for receiving data items for transfer to or from the memory blocks, wherein in two consecutive clock cycles at least a first and a second write data items corresponding to a first write burst operation are capable of being transferred sequentially to the memory circuit via the data bus and at least a first and second read data items corresponding to a first read burst operation are capable of being provided sequentially by the memory circuit via the data bus, and wherein the data bus is capable of receiving data corresponding to the write burst operation and providing data corresponding to the read burst operation with no dead cycles therebetween; and
further includingan output circuit for receiving the at least first and second read data items from respective at least two memory blocks in the first read burst operation and allowing the first read data item to be provided on the data bus half a clock cycle after the first read burst operation is initiated, and allowing the second read data item to be provided on the data bus one clock cycle after the first read burst operation is initiated; and
at least two registers for providing both a burst address received at the address bus and at least one read/write control signal received at least one input terminal of the memory circuit to the at least two memory blocks sequentially in one clock cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A synchronous memory circuit comprising:
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an address bus for receiving an address;
at least two memory blocks each of which is capable to be accessed at said address;
a data bus for receiving data items for transfer to or from the memory blocks, wherein in two consecutive clock cycles at least a first and a second write data items corresponding to a first write burst operation are capable of being transferred sequentially to the memory circuit via the data bus and at least a first and second read data items corresponding to a first read burst operation are capable of being provided sequentially by the memory circuit via the data bus, wherein in the first write burst operation at least a third and fourth write data items are written to respective at least two memory blocks, the third and fourth write data items corresponding to a last write burst operation prior to the first write burst operation, and wherein the data bus is capable of receiving data corresponding to the write burst operation and providing data corresponding to the read burst operation with no dead cycles therebetween; and
further comprising a multiplexer for selecting for transfer to the at least two memory blocks one of a write burst address stored in a first register and a burst address provided on the address bus, wherein in the first write burst operation the multiplexer selects a first write burst address stored in the first register, the first write burst address corresponding to the last write burst operation, and in the first read burst operation the multiplexer selects a first read burst address provided on the address bus. - View Dependent Claims (24)
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25. A synchronous memory circuit comprising:
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an address bus for receiving an address;
at least two memory blocks each of which is capable to be accessed at said address;
a data bus for receiving data items for transfer to or from the memory blocks, wherein in two consecutive clock cycles at least a first and a second write data items corresponding to a first write burst operation are capable of being transferred sequentially to the memory circuit via the data bus and at least a first and second read data items corresponding to a first read burst operation are capable of being provided sequentially by the memory circuit via the data bus, and wherein the data bus is capable of receiving data corresponding to the write burst operation and providing data corresponding to the read burst operation with no dead cycles therebetween; and
further comprising a circuit for generating an echo clock signal from the clock signal such that the echo clock signal is active only when a read data item is provided on the data bus. - View Dependent Claims (26)
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27. A method of accessing a synchronous memory circuit, the method comprising:
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(A) initiating a first write burst operation for sequentially transferring at least a first and second write data items to the memory circuit in a first clock cycle; and
(B) initiating a first read burst operation for sequentially transferring at least a first and second read data items from the memory circuit in a second clock cycle, wherein the first and second clock cycles are two consecutive clock cycles; (C) generating an echo clock signal from a clock signal, the echo clock signal being active only when a read data item is read from the memory circuit. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35)
act (D) comprises; (F) asserting a read/write control signal on an input terminal of the memory circuit to indicate a write burst operation prior to a rising edge of the third clock cycle; and
(G) providing a first write burst address on an address bus of the memory circuit prior to the rising edge of the third clock cycle, and act (E) comprises; (H) asserting the read/write control signal to indicate a read burst operation prior to a rising edge of the fourth clock cycle; and
(I) providing a first read burst address on the address bus prior to the rising edge of the fourth clock cycle.
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30. The method of claim 27 wherein the memory circuit includes at least two memory blocks, the method further comprising:
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(J) transferring at least a third and fourth data items corresponding to a second burst operation to or from respective at least two memory blocks; and
(K) transferring at least a fifth and sixth data items corresponding to a third burst operation to or from respective at least two memory blocks, wherein acts (J) and (K) are carried out in two and half consecutive clock cycles.
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31. The method of claim 30 wherein said transferring the at least third and fourth data items to or from respective at least two memory blocks overlaps with said transferring the at least fifth and sixth data items to or from respective at least two memory blocks during half a clock cycle.
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32. The method of claim 27 wherein the memory circuit includes two memory blocks and act (A) comprises:
(L) writing at least a third and fourth write data items to respective two memory blocks so that writing the third write data item overlaps with writing the fourth write data item, the at least third and fourth write data items corresponding to a last write burst operation prior to the first write burst operation.
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33. The method of claim 32 wherein act (L) comprises:
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(M) writing the third write data item in one clock cycle; and
(N) writing the fourth write data item in one clock cycle, wherein said writing the third write data item overlaps with said writing the fourth write data item during half a clock cycle.
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34. The method of claim 27 wherein the memory circuit includes two memory blocks and act (B) comprises:
(O) reading the at least first and second read data items from respective two memory blocks so that reading the first read data item overlaps with reading the second read data item.
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35. The method of claim 34 wherein act (O) comprises:
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(P) reading the first read data item in one clock cycle; and
(Q) reading the second read data item in one clock cycle, wherein said reading the first read data item overlaps with said reading the second read data item during half a clock cycle.
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36. A synchronous memory circuit comprising:
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an address bus for receiving a burst address;
two memory blocks;
data bus for transferring data corresponding to the burst address to or from the two memory blocks;
a control input terminal for receiving a read/write control signal for indicating a read burst or a write burst operation, wherein a burst operation is initiated upon a rising edge of a clock cycle by asserting the read/write control signal to indicate a write burst or a read burst operation and providing an address at the address bus both prior to the rising edge of the clock cycle;
an output circuit for receiving two read data items from respective two memory blocks in a first read burst operation and allowing one of the two read data items to be provided on the data bus half a clock cycle after the first read burst operation is initiated, and allowing the other one of the two read data items to be provided on the data bus one clock cycle after the first read burst operation is initiated; and
a first and second registers for storing respective two write data items provided on the data bus in a first write burst operation, wherein one of the two write data items is written to one of the two memory blocks at the initiation of a next write burst operation following the first write burst operation, and the other one of the two write data items is written to the other one of the two memory blocks half a clock cycle after the initiation of the next write burst operation, wherein in two consecutive clock cycles the two write data items are capable of being transferred to the memory circuit via the data bus and the two read data items are capable of being transferred from the memory circuit via the data bus. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43)
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44. A memory circuit, comprising:
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a first register that receives and stores an address on a first transition of a clock signal;
a second register that receives and stores the address from the first register on a second transition of the clock signal;
a first memory block coupled to receive the address from the first register; and
a second memory block coupled to receive the address from the second register, wherein a first data is read into the first memory block and a second data is read into the second memory block in one cycle of the clock signal when a write signal is associated with the address, the first data and the second data each being part of a single data word. - View Dependent Claims (45, 50, 51, 52)
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46. A memory circuit, comprising:
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a first register that receives and stores an address on a first transition of a clock signal;
a second register that receives and stores the address from the first register on a second transition of the clock signal;
a first memory block coupled to receive the address from the first register; and
a second memory block coupled to receive the address from the second register, wherein a first data is read out from the first memory block and second data is read out from the second memory block in one cycle of the clock signal when a read signal is associated with the address, the first data and the second data each being part of a single data word.
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47. A memory circuit, comprising:
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a first register that receives and stores an address on a first transition of a clock signal;
a second register that receives and stores the address from the first register on a second transition of the clock signal;
a first memory block coupled to receive the address from the first register; and
a second memory block coupled to receive the address from the second register, wherein a read access can occur in a first cycle of the clock signal and a write access can occur in a second cycle immediately following the first cycle with no dead cycles between.
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48. A memory circuit, comprising:
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a first register that receives and stores an address on a first transition of a clock signal;
a second register that receives and stores the address from the first register on a second transition of the clock signal;
a first memory block coupled to receive the address from the first register; and
a second memory block coupled to receive the address from the second register, wherein a write access can occur in a first cycle of the clock signal and a read access can occur in a second cycle immediately following the first cycle with no dead cycles between.
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49. A memory circuit, comprising:
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a first register that receives and stores an address on a first transition of a clock signal;
a second register that receives and stores the address from the first register on a second transition of the clock signal;
a first memory block coupled to receive the address from the first register; and
a second memory block coupled to receive the address from the second register, wherein each memory location of the first memory block stores a first portion of a data word and a corresponding memory location of the second memory block stores a second portion of a data word.
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Specification